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| author | Paolo Bonzini <pbonzini@redhat.com> | 2022-12-27 07:56:16 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-01-24 06:08:01 -0500 |
| commit | f15a87c006901e02727bf8ac75b0251cdf8e0ecc (patch) | |
| tree | 836b6213ec9a495610aab6d2181d44d4a05f3214 /Documentation/virt | |
| parent | dc7c31e922787466957cadf2c0ad21c0f9a4091f (diff) | |
| parent | 72c70ceeaf59330b1d63380add768bdbdeb24b7c (diff) | |
| download | linux-stable-f15a87c006901e02727bf8ac75b0251cdf8e0ecc.tar.gz linux-stable-f15a87c006901e02727bf8ac75b0251cdf8e0ecc.tar.bz2 linux-stable-f15a87c006901e02727bf8ac75b0251cdf8e0ecc.zip | |
Merge branch 'kvm-lapic-fix-and-cleanup' into HEAD
The first half or so patches fix semi-urgent, real-world relevant APICv
and AVIC bugs.
The second half fixes a variety of AVIC and optimized APIC map bugs
where KVM doesn't play nice with various edge cases that are
architecturally legal(ish), but are unlikely to occur in most real world
scenarios
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'Documentation/virt')
| -rw-r--r-- | Documentation/virt/kvm/x86/errata.rst | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/virt/kvm/x86/errata.rst b/Documentation/virt/kvm/x86/errata.rst index 410e0aa63493..49a05f24747b 100644 --- a/Documentation/virt/kvm/x86/errata.rst +++ b/Documentation/virt/kvm/x86/errata.rst @@ -37,3 +37,14 @@ Nested virtualization features ------------------------------ TBD + +x2APIC +------ +When KVM_X2APIC_API_USE_32BIT_IDS is enabled, KVM activates a hack/quirk that +allows sending events to a single vCPU using its x2APIC ID even if the target +vCPU has legacy xAPIC enabled, e.g. to bring up hotplugged vCPUs via INIT-SIPI +on VMs with > 255 vCPUs. A side effect of the quirk is that, if multiple vCPUs +have the same physical APIC ID, KVM will deliver events targeting that APIC ID +only to the vCPU with the lowest vCPU ID. If KVM_X2APIC_API_USE_32BIT_IDS is +not enabled, KVM follows x86 architecture when processing interrupts (all vCPUs +matching the target APIC ID receive the interrupt). |