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| author | Allen-KH Cheng <allen-kh.cheng@mediatek.com> | 2024-01-27 10:42:58 +0200 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2024-02-12 13:37:00 +0100 |
| commit | f10a5fbc14cb20f1254f7e9a5917896ef423c662 (patch) | |
| tree | b11ad24a9b7b925bf74f6f79d354cfdb9a0c6522 /arch/arm64/boot/dts/mediatek/mt8186.dtsi | |
| parent | ebd27256bd14a5458c8cefa4a4d5169ab3fc6c09 (diff) | |
| download | linux-stable-f10a5fbc14cb20f1254f7e9a5917896ef423c662.tar.gz linux-stable-f10a5fbc14cb20f1254f7e9a5917896ef423c662.tar.bz2 linux-stable-f10a5fbc14cb20f1254f7e9a5917896ef423c662.zip | |
arm64: dts: mediatek: mt8186: Add jpgenc node
Add JPEG encoder node.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Max Staudt <mstaudt@chromium.org>
Tested-by: Max Staudt <mstaudt@chromium.org>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
[eugen.hristev@collabora.com: minor cleanup]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240127084258.68302-2-eugen.hristev@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8186.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8186.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index e8dfb9c55e5f..adaf5e57fac5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -2018,6 +2018,19 @@ mediatek,scp = <&scp>; }; + jpgenc: jpeg-encoder@17030000 { + compatible = "mediatek,mt8186-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x17030000 0 0x10000>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_CKE2_JPGENC>; + clock-names = "jpgenc"; + iommus = <&iommu_mm IOMMU_PORT_L7_JPGENC_Y_RDMA>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_C_RDMA>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_Q_TABLE>, + <&iommu_mm IOMMU_PORT_L7_JPGENC_BSDMA>; + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8186-camsys"; reg = <0 0x1a000000 0 0x1000>; |