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| author | Yunfeng Ye <yeyunfeng@huawei.com> | 2021-12-09 09:46:03 +0800 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2021-12-10 18:24:20 +0000 |
| commit | 386a74677be13175b5626f094ef37808c45f48b8 (patch) | |
| tree | 1a1a0c2cb1d269dd7bea2a1b517a8da75b0f9fc5 /arch/arm64 | |
| parent | a3a5b763410c7bceacf41a52071134d9dc26202a (diff) | |
| download | linux-stable-386a74677be13175b5626f094ef37808c45f48b8.tar.gz linux-stable-386a74677be13175b5626f094ef37808c45f48b8.tar.bz2 linux-stable-386a74677be13175b5626f094ef37808c45f48b8.zip | |
arm64: mm: Use asid feature macro for cheanup
The commit 95b54c3e4c92 ("KVM: arm64: Add feature register flag
definitions") introduce the ID_AA64MMFR0_ASID_8 and ID_AA64MMFR0_ASID_16
macros.
We can use these macros for cheanup in get_cpu_asid_bits().
No functional change.
Signed-off-by: Yunfeng Ye <yeyunfeng@huawei.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Link: https://lore.kernel.org/r/f71c75d3-735e-b32a-8414-b3e513c77240@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/mm/context.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index bbc2708fe928..b8b4cf0bcf39 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -50,10 +50,10 @@ static u32 get_cpu_asid_bits(void) pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", smp_processor_id(), fld); fallthrough; - case 0: + case ID_AA64MMFR0_ASID_8: asid = 8; break; - case 2: + case ID_AA64MMFR0_ASID_16: asid = 16; } |