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author | Aaro Koskinen <aaro.koskinen@iki.fi> | 2019-01-27 23:28:33 +0200 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-02-15 08:10:11 +0100 |
commit | 264b26201a2245c85a7dddded0493fa9194b210d (patch) | |
tree | c77f42dc9456e10c39f009f0ac53148ba8814c46 /arch/mips | |
parent | 384cc5fd6727317e3c2f3cef697c4fb60f30e2b5 (diff) | |
download | linux-stable-264b26201a2245c85a7dddded0493fa9194b210d.tar.gz linux-stable-264b26201a2245c85a7dddded0493fa9194b210d.tar.bz2 linux-stable-264b26201a2245c85a7dddded0493fa9194b210d.zip |
MIPS: OCTEON: don't set octeon_dma_bar_type if PCI is disabled
commit dcf300a69ac307053dfb35c2e33972e754a98bce upstream.
Don't set octeon_dma_bar_type if PCI is disabled. This avoids creation
of the MSI irqchip later on, and saves a bit of memory.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: a214720cbf50 ("Disable MSI also when pcie-octeon.pcie_disable on")
Cc: stable@vger.kernel.org # v3.3+
Cc: linux-mips@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/pci/pci-octeon.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 5017d5843c5a..fc29b85cfa92 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -568,6 +568,11 @@ static int __init octeon_pci_setup(void) if (octeon_has_feature(OCTEON_FEATURE_PCIE)) return 0; + if (!octeon_is_pci_host()) { + pr_notice("Not in host mode, PCI Controller not initialized\n"); + return 0; + } + /* Point pcibios_map_irq() to the PCI version of it */ octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; @@ -579,11 +584,6 @@ static int __init octeon_pci_setup(void) else octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; - if (!octeon_is_pci_host()) { - pr_notice("Not in host mode, PCI Controller not initialized\n"); - return 0; - } - /* PCI I/O and PCI MEM values */ set_io_port_base(OCTEON_PCI_IOSPACE_BASE); ioport_resource.start = 0; |