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| author | Jisheng Zhang <jszhang@kernel.org> | 2024-07-21 01:06:59 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-09-15 20:58:25 -0700 |
| commit | 8f1534e7440382d118c3d655d3a6014128b2086d (patch) | |
| tree | 125343c989be1ae407db466d0e9ca5edd5f4eff9 /arch/riscv | |
| parent | 7e340f4fad46b766705be96f5d1c764a397a7a36 (diff) | |
| download | linux-stable-8f1534e7440382d118c3d655d3a6014128b2086d.tar.gz linux-stable-8f1534e7440382d118c3d655d3a6014128b2086d.tar.bz2 linux-stable-8f1534e7440382d118c3d655d3a6014128b2086d.zip | |
riscv: avoid Imbalance in RAS
Inspired by[1], modify the code to remove the code of modifying ra to
avoid imbalance RAS (return address stack) which may lead to incorret
predictions on return.
Link: https://lore.kernel.org/linux-riscv/20240607061335.2197383-1-cyrilbur@tenstorrent.com/ [1]
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Cyril Bur <cyrilbur@tenstorrent.com>
Link: https://lore.kernel.org/r/20240720170659.1522-1-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/kernel/entry.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index fc41472d512e..c200d329d4bd 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -326,8 +326,8 @@ SYM_CODE_START(ret_from_fork) jalr s0 1: move a0, sp /* pt_regs */ - la ra, ret_from_exception - tail syscall_exit_to_user_mode + call syscall_exit_to_user_mode + j ret_from_exception SYM_CODE_END(ret_from_fork) #ifdef CONFIG_IRQ_STACKS |