summaryrefslogtreecommitdiffstats
path: root/arch/sh/include
diff options
context:
space:
mode:
authorChristoph Hellwig <hch@lst.de>2020-07-14 14:18:51 +0200
committerRich Felker <dalias@libc.org>2020-08-14 22:05:15 -0400
commit13f1fc870dd747131f21ba6f20dc0d81cc5d4474 (patch)
tree4d5d6ebb959a02d29f91753442c7a28cc2ac597b /arch/sh/include
parent3eef6b74d9fecf18b03db26584cc66928972a60b (diff)
downloadlinux-stable-13f1fc870dd747131f21ba6f20dc0d81cc5d4474.tar.gz
linux-stable-13f1fc870dd747131f21ba6f20dc0d81cc5d4474.tar.bz2
linux-stable-13f1fc870dd747131f21ba6f20dc0d81cc5d4474.zip
sh: move the ioremap implementation out of line
Move the internal implementation details of ioremap out of line, no need to expose any of this to drivers for a slow path API. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/io.h101
1 files changed, 15 insertions, 86 deletions
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 357a7e0c86d6..da08a61a2f7d 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -242,109 +242,38 @@ unsigned long long poke_real_address_q(unsigned long long addr,
#define phys_to_virt(address) (__va(address))
#endif
-/*
- * On 32-bit SH, we traditionally have the whole physical address space
- * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
- * not need to do anything but place the address in the proper segment.
- * This is true for P1 and P2 addresses, as well as some P3 ones.
- * However, most of the P3 addresses and newer cores using extended
- * addressing need to map through page tables, so the ioremap()
- * implementation becomes a bit more complicated.
- *
- * See arch/sh/mm/ioremap.c for additional notes on this.
- *
- * We cheat a bit and always return uncachable areas until we've fixed
- * the drivers to handle caching properly.
- *
- * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
- * doesn't exist, so everything must go through page tables.
- */
#ifdef CONFIG_MMU
+void iounmap(void __iomem *addr);
void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
pgprot_t prot, void *caller);
-void iounmap(void __iomem *addr);
-
-static inline void __iomem *
-__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
-{
- return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
-}
-
-static inline void __iomem *
-__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
-{
-#ifdef CONFIG_29BIT
- phys_addr_t last_addr = offset + size - 1;
-
- /*
- * For P1 and P2 space this is trivial, as everything is already
- * mapped. Uncached access for P1 addresses are done through P2.
- * In the P3 case or for addresses outside of the 29-bit space,
- * mapping must be done by the PMB or by using page tables.
- */
- if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
- u64 flags = pgprot_val(prot);
-
- /*
- * Anything using the legacy PTEA space attributes needs
- * to be kicked down to page table mappings.
- */
- if (unlikely(flags & _PAGE_PCC_MASK))
- return NULL;
- if (unlikely(flags & _PAGE_CACHABLE))
- return (void __iomem *)P1SEGADDR(offset);
-
- return (void __iomem *)P2SEGADDR(offset);
- }
-
- /* P4 above the store queues are always mapped. */
- if (unlikely(offset >= P3_ADDR_MAX))
- return (void __iomem *)P4SEGADDR(offset);
-#endif
-
- return NULL;
-}
-
-static inline void __iomem *
-__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
-{
- void __iomem *ret;
-
- ret = __ioremap_trapped(offset, size);
- if (ret)
- return ret;
-
- ret = __ioremap_29bit(offset, size, prot);
- if (ret)
- return ret;
-
- return __ioremap(offset, size, prot);
-}
-#else
-#define __ioremap(offset, size, prot) ((void __iomem *)(offset))
-#define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset))
-static inline void iounmap(void __iomem *addr) {}
-#endif /* CONFIG_MMU */
static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
{
- return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
+ return __ioremap_caller(offset, size, PAGE_KERNEL_NOCACHE,
+ __builtin_return_address(0));
}
static inline void __iomem *
ioremap_cache(phys_addr_t offset, unsigned long size)
{
- return __ioremap_mode(offset, size, PAGE_KERNEL);
+ return __ioremap_caller(offset, size, PAGE_KERNEL,
+ __builtin_return_address(0));
}
#define ioremap_cache ioremap_cache
#ifdef CONFIG_HAVE_IOREMAP_PROT
-static inline void __iomem *
-ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
+static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
+ unsigned long flags)
{
- return __ioremap_mode(offset, size, __pgprot(flags));
+ return __ioremap_caller(offset, size, __pgprot(flags),
+ __builtin_return_address(0));
}
-#endif
+#endif /* CONFIG_HAVE_IOREMAP_PROT */
+
+#else /* CONFIG_MMU */
+#define iounmap(addr) do { } while (0)
+#define ioremap(offset, size) ((void __iomem *)(unsigned long)(offset))
+#endif /* CONFIG_MMU */
#define ioremap_uc ioremap