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authorRajendra Nayak <rnayak@codeaurora.org>2020-08-12 15:52:10 +0530
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-10-29 10:12:03 +0100
commit25fbbd5f9ece50e49662856a08018abdbf9b2860 (patch)
tree29d6c6317b2375fa934b2012ee0d5b104c76589f /arch
parentd1c07decc8d6081f516d19b8b248514e1043367d (diff)
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arm64: dts: sdm845: Fixup OPP table for all qup devices
[ Upstream commit e0b760a5f6c9e54db8bd22b1d6b19223e6b92264 ] This OPP table was based on the clock VDD-FMAX tables seen in downstream code, however it turns out the downstream clock driver does update these tables based on later/production rev of the chip and whats seen in the tables belongs to an early engineering rev of the SoC. Fix up the OPP tables such that it now matches with the production rev of sdm845 SoC. Tested-by: Amit Pundir <amit.pundir@linaro.org> Tested-by: John Stultz <john.stultz@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Fixes: 13cadb34e593 ("arm64: dts: sdm845: Add OPP table for all qup devices") Reported-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1597227730-16477-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/qcom/sdm845.dtsi9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2884577dcb77..eca81cffd2c1 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1093,8 +1093,8 @@
qup_opp_table: qup-opp-table {
compatible = "operating-points-v2";
- opp-19200000 {
- opp-hz = /bits/ 64 <19200000>;
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
@@ -1107,6 +1107,11 @@
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
};
qupv3_id_0: geniqup@8c0000 {