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| author | Sylvain Lemieux <slemieux@tycoint.com> | 2016-02-10 13:52:32 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-02-10 12:45:16 -0800 |
| commit | 7e0810c9485ce696df3813574bca44139f6eb0c8 (patch) | |
| tree | 713ed9293393277038ffcb223b1d8fed65356e9f /drivers/clk/nxp | |
| parent | 58bb621536d1f64db619744c85dcbb94705eda85 (diff) | |
| download | linux-stable-7e0810c9485ce696df3813574bca44139f6eb0c8.tar.gz linux-stable-7e0810c9485ce696df3813574bca44139f6eb0c8.tar.bz2 linux-stable-7e0810c9485ce696df3813574bca44139f6eb0c8.zip | |
clk: lpc32xx: add HCLK PLL output configuration
This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.
If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.
The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/nxp')
| -rw-r--r-- | drivers/clk/nxp/clk-lpc32xx.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index 981ff0dd88b4..48b3a11aa09a 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -87,7 +87,7 @@ enum { enum { /* Start from the last defined clock in dt bindings */ - LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_ADC + 1, + LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_HCLK_PLL + 1, LPC32XX_CLK_ADC_RTC, LPC32XX_CLK_TEST1, LPC32XX_CLK_TEST2, @@ -96,7 +96,6 @@ enum { LPC32XX_CLK_OSC, LPC32XX_CLK_SYS, LPC32XX_CLK_PLL397X, - LPC32XX_CLK_HCLK_PLL, LPC32XX_CLK_HCLK_DIV_PERIPH, LPC32XX_CLK_HCLK_DIV, LPC32XX_CLK_HCLK, @@ -1526,9 +1525,6 @@ static void __init lpc32xx_clk_init(struct device_node *np) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - /* For 13MHz osc valid output range of PLL is from 156MHz to 266.5MHz */ - clk_set_rate(clk[LPC32XX_CLK_HCLK_PLL], 208000000); - /* Set 48MHz rate of USB PLL clock */ clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000); |