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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2018-06-08 16:04:34 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-06-08 19:30:02 +0100 |
| commit | f6b1e35f3e47f40d18fe50a52c09a618ec703c1b (patch) | |
| tree | 5cd0b2367b73bcebfe5e2f7b74dd14b4e8258b59 /drivers/gpu/drm/i915/i915_gem_gtt.c | |
| parent | b4e2727df2713a5aea9de6364f7a943147ceef92 (diff) | |
| download | linux-stable-f6b1e35f3e47f40d18fe50a52c09a618ec703c1b.tar.gz linux-stable-f6b1e35f3e47f40d18fe50a52c09a618ec703c1b.tar.bz2 linux-stable-f6b1e35f3e47f40d18fe50a52c09a618ec703c1b.zip | |
drm/i915/gtt: Remove redundant hsw_mm_switch()
hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the
redundant specialism.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180608150435.15010-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index ae3b24095d04..df0ea66ba68c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1718,28 +1718,6 @@ static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt) return ppgtt->pd.base.ggtt_offset << 10; } -static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, - struct i915_request *rq) -{ - struct intel_engine_cs *engine = rq->engine; - u32 *cs; - - /* NB: TLBs must be flushed and invalidated before a switch */ - cs = intel_ring_begin(rq, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_LOAD_REGISTER_IMM(2); - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); - *cs++ = PP_DIR_DCLV_2G; - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); - *cs++ = get_pd_offset(ppgtt); - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - - return 0; -} - static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, struct i915_request *rq) { @@ -2048,8 +2026,6 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) ppgtt->vm.pte_encode = ggtt->vm.pte_encode; if (intel_vgpu_active(i915) || IS_GEN6(i915)) ppgtt->switch_mm = gen6_mm_switch; - else if (IS_HASWELL(i915)) - ppgtt->switch_mm = hsw_mm_switch; else if (IS_GEN7(i915)) ppgtt->switch_mm = gen7_mm_switch; else |