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| author | Shaokun Zhang <zhangshaokun@hisilicon.com> | 2017-10-19 19:05:20 +0800 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-10-19 17:06:35 +0100 |
| commit | 904dcf03f086a2e3b9d1e02cb57c43ea2e588c8c (patch) | |
| tree | c9a4482bd8c5b33d64bc1220254d266bf3d6072d /drivers/perf/hisilicon/Makefile | |
| parent | 2bab3cf9104c5ab80a1b9c706d81d997548401e4 (diff) | |
| download | linux-stable-904dcf03f086a2e3b9d1e02cb57c43ea2e588c8c.tar.gz linux-stable-904dcf03f086a2e3b9d1e02cb57c43ea2e588c8c.tar.bz2 linux-stable-904dcf03f086a2e3b9d1e02cb57c43ea2e588c8c.zip | |
perf: hisi: Add support for HiSilicon SoC DDRC PMU driver
This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
DDRC has own control, counter and interrupt registers and is an separate
PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
mapped to 8-events by hardware, it assumes that counter index is equal
to event code (0 - 7) in DDRC PMU driver. Interrupt is supported to
handle counter (32-bits) overflow.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/perf/hisilicon/Makefile')
| -rw-r--r-- | drivers/perf/hisilicon/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile index a72afe84d034..2621d51ae87a 100644 --- a/drivers/perf/hisilicon/Makefile +++ b/drivers/perf/hisilicon/Makefile @@ -1 +1 @@ -obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o +obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o |