diff options
author | Neil Armstrong <neil.armstrong@linaro.org> | 2024-08-29 10:44:30 +0200 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2024-08-29 10:48:28 -0700 |
commit | aa2eb2c4356affa2799efd95a4ee2d239ca630f8 (patch) | |
tree | f94cd79779b553e57df3ba33e15fae139b7a9a3e /drivers/spi/spi-dw-bt1.c | |
parent | 7b6dfa1bbe7f727315d2e05a2fc8e4cfeb779156 (diff) | |
download | linux-stable-aa2eb2c4356affa2799efd95a4ee2d239ca630f8.tar.gz linux-stable-aa2eb2c4356affa2799efd95a4ee2d239ca630f8.tar.bz2 linux-stable-aa2eb2c4356affa2799efd95a4ee2d239ca630f8.zip |
clk: qcom: gcc-sm8650: Don't use shared clk_ops for QUPs
The QUPs aren't shared in a way that requires parking the RCG at an
always on parent in case some other entity turns on the clk. The
hardware is capable of setting a new frequency itself with the DFS mode,
so parking is unnecessary. Furthermore, there aren't any GDSCs for these
devices, so there isn't a possibility of the GDSC turning on the clks
for housekeeping purposes.
Like for the SM8550 GCC QUP clocks at [1], do not use shared clk_ops for QUPs.
[1] https://lore.kernel.org/all/20240827231237.1014813-3-swboyd@chromium.org/
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240829-topic-sm8650-upstream-fix-qup-clk-rcg-shared-v1-1-7ecdbc672187@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/spi/spi-dw-bt1.c')
0 files changed, 0 insertions, 0 deletions