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| author | Maxime Chevallier <maxime.chevallier@smile.fr> | 2017-11-27 15:16:32 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-11-27 15:23:30 +0000 |
| commit | 251c201bf4f8b5bf4f1ccb4f8920eed2e1f57580 (patch) | |
| tree | 434c3ee288b76e5343c08b527e5958080bb84eef /drivers/spi | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
| download | linux-stable-251c201bf4f8b5bf4f1ccb4f8920eed2e1f57580.tar.gz linux-stable-251c201bf4f8b5bf4f1ccb4f8920eed2e1f57580.tar.bz2 linux-stable-251c201bf4f8b5bf4f1ccb4f8920eed2e1f57580.zip | |
spi: a3700: Fix clk prescaling for coefficient over 15
The Armada 3700 SPI controller has 2 ranges of prescaler coefficients.
One ranging from 0 to 15 by steps of 1, and one ranging from 0 to 30 by
steps of 2.
This commit fixes the prescaler coefficients that are over 15 so that it
uses the correct range of values. The prescaling coefficient is rounded
to the upper value if it is odd.
This was tested on Espressobin with spidev and a locigal analyser.
Signed-off-by: Maxime Chevallier <maxime.chevallier@smile.fr>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-armada-3700.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c index 77fe55ce790c..d65345312527 100644 --- a/drivers/spi/spi-armada-3700.c +++ b/drivers/spi/spi-armada-3700.c @@ -79,6 +79,7 @@ #define A3700_SPI_BYTE_LEN BIT(5) #define A3700_SPI_CLK_PRESCALE BIT(0) #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) +#define A3700_SPI_CLK_EVEN_OFFS (0x10) #define A3700_SPI_WFIFO_THRS_BIT 28 #define A3700_SPI_RFIFO_THRS_BIT 24 @@ -220,6 +221,13 @@ static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); + /* For prescaler values over 15, we can only set it by steps of 2. + * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to + * 30. We only use this range from 16 to 30. + */ + if (prescale > 15) + prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2); + val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); val = val & ~A3700_SPI_CLK_PRESCALE_MASK; |