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author | Philipp Zabel <p.zabel@pengutronix.de> | 2014-02-24 14:51:49 +0100 |
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committer | Shawn Guo <shawn.guo@linaro.org> | 2014-03-05 10:40:47 +0800 |
commit | ef3adc187ca6418a376774ebf55d1258d1dc2c31 (patch) | |
tree | 7d4b9a8feabbfc8320c943eb8c54a06ec85b7712 /include/linux/mfd | |
parent | 8d9ee21e98205eebc7fc6caf08a764c9e12c7d68 (diff) | |
download | linux-stable-ef3adc187ca6418a376774ebf55d1258d1dc2c31.tar.gz linux-stable-ef3adc187ca6418a376774ebf55d1258d1dc2c31.tar.bz2 linux-stable-ef3adc187ca6418a376774ebf55d1258d1dc2c31.zip |
ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
Masks for IPU AXI transaction QoS settings
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'include/linux/mfd')
-rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index 866e355fa409..ff44374a1a4e 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -242,6 +242,24 @@ #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) +#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) +#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK (0xf << 8) +#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK (0xf << 12) +#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK (0xf << 16) +#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK (0xf << 20) +#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24) +#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK (0xf << 28) + +#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK (0xf << 0) +#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK (0xf << 4) +#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK (0xf << 8) +#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK (0xf << 12) +#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK (0xf << 16) +#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK (0xf << 20) +#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24) +#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28) + #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) #define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) |