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authorDuc Dang <dhdang@apm.com>2016-12-01 18:27:07 -0800
committerBjorn Helgaas <helgaas@kernel.org>2016-12-06 13:45:50 -0600
commitc5d4603961009c39de94725213d8b5420f110f9e (patch)
tree28d5b46fed39d45cd2b7a28c8c73f161527902bd /include/linux/pci-ecam.h
parent648d93fc77da4f655cf13108417f33c91d745e2c (diff)
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PCI: Add MCFG quirks for X-Gene host controller
PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to configure additional controller's register to address device at bus:dev:function. Add a quirk to discover controller MMIO register space and configure controller registers to select and address the target secondary device. The quirk will only be applied for X-Gene PCIe MCFG table with OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs). Tested-by: Jon Masters <jcm@redhat.com> Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/linux/pci-ecam.h')
-rw-r--r--include/linux/pci-ecam.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index 00eb8eb774e2..f0d2b9451270 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -64,6 +64,8 @@ extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
+extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
+extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
#endif
#ifdef CONFIG_PCI_HOST_GENERIC