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| author | Andrew Jones <ajones@ventanamicro.com> | 2025-03-04 13:00:20 +0100 |
|---|---|---|
| committer | Alexandre Ghiti <alexghiti@rivosinc.com> | 2025-03-19 14:23:30 +0000 |
| commit | 05ee21f0fcb8ca29bf42bd6cbce109f2e49c167f (patch) | |
| tree | 6d7bd8c95f88b6c89cdeb9c1f20e5cd2d51d1bf6 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 813d39baee3229d31420af61460b97f4fafdd352 (diff) | |
| download | linux-stable-05ee21f0fcb8ca29bf42bd6cbce109f2e49c167f.tar.gz linux-stable-05ee21f0fcb8ca29bf42bd6cbce109f2e49c167f.tar.bz2 linux-stable-05ee21f0fcb8ca29bf42bd6cbce109f2e49c167f.zip | |
riscv: Fix set up of cpu hotplug callbacks
CPU hotplug callbacks should be set up even if we detected all
current cpus emulate misaligned accesses, since we want to
ensure our expectations of all cpus emulating is maintained.
Fixes: 6e5ce7f2eae3 ("riscv: Decouple emulated unaligned accesses from access speed")
Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe")
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20250304120014.143628-15-ajones@ventanamicro.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions