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-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328.dtsi10
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi10
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-firefly.dts8
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts4
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi8
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts25
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi4
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts12
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi23
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi36
10 files changed, 111 insertions, 29 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index be2bfbc6b483..b8e9da15e00c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -595,6 +595,8 @@
reg = <0x0 0xff330200 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265e_mmu";
+ clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -604,6 +606,8 @@
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -613,6 +617,8 @@
reg = <0x0 0xff350800 0x0 0x40>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -622,6 +628,8 @@
reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvdec_mmu";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -631,6 +639,8 @@
reg = <0x0 0xff373f00 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 03458ac44201..ad91ced78649 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -742,6 +742,8 @@
reg = <0x0 0xff900800 0x0 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -752,6 +754,8 @@
<0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_mmu";
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
@@ -762,6 +766,8 @@
reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -772,6 +778,8 @@
<0x0 0xff9a0480 0x0 0x40>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -782,6 +790,8 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu", "vdpu_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index 4f28628aa091..2a352763c848 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -662,6 +662,14 @@
status = "okay";
};
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
index 191a6bcb1704..82179125bfb7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
@@ -255,7 +255,7 @@ ap_i2c_dig: &i2c2 {
&ap_i2c_tp {
trackpad@4a {
- compatible = "atmel,atmel_mxt_tp";
+ compatible = "atmel,maxtouch";
reg = <0x4a>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_int_l>;
@@ -271,7 +271,7 @@ ap_i2c_dig: &i2c2 {
&ap_i2c_ts {
touchscreen@4b {
- compatible = "atmel,atmel_mxt_ts";
+ compatible = "atmel,maxtouch";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int_l>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 18f546f2dfd1..f49bfab75dd0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -588,7 +588,9 @@
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
- <&cru ACLK_VIO>;
+ <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
+ <&cru ACLK_GIC_PRE>,
+ <&cru PCLK_DDR>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
@@ -597,7 +599,9 @@
<100000000>, <100000000>,
<50000000>, <800000000>,
<100000000>, <50000000>,
- <400000000>;
+ <400000000>, <400000000>,
+ <200000000>,
+ <200000000>;
};
&emmc_phy {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
index 7d3e8bfd51dd..e0afdd8b62bd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
@@ -143,6 +143,11 @@
};
};
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@@ -246,6 +251,10 @@
status = "okay";
};
+&tcphy0 {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
@@ -281,3 +290,19 @@
&usb_host0_ohci {
status = "okay";
};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
index 4a2d06abe9c1..14a0f1998639 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
@@ -527,6 +527,10 @@
};
};
+&tcphy1 {
+ status = "okay";
+};
+
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
index 56952d1a3fb8..ad7548d3b93d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
@@ -190,6 +190,18 @@
status = "okay";
};
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index e5daed7d2026..941b627094d7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -471,21 +471,6 @@
gpio1830-supply = <&vcc_3v0>;
};
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
- assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
- assigned-clock-rates = <100000000>;
- ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- status = "okay";
-};
-
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
@@ -560,6 +545,14 @@
status = "okay";
};
+&tcphy0 {
+ status = "okay";
+};
+
+&tcphy1 {
+ status = "okay";
+};
+
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4550c0f82be9..e0040b648f43 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -312,6 +312,8 @@
reg = <0x0 0xfe320000 0x0 0x4000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
max-frequency = <150000000>;
+ assigned-clocks = <&cru HCLK_SD>;
+ assigned-clock-rates = <200000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -411,8 +413,8 @@
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy0_otg>;
- phy-names = "usb2-phy";
+ phys = <&u2phy0_otg>, <&tcphy0_usb3>;
+ phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -444,8 +446,8 @@
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy1_otg>;
- phy-names = "usb2-phy";
+ phys = <&u2phy1_otg>, <&tcphy1_usb3>;
+ phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -461,8 +463,8 @@
compatible = "rockchip,rk3399-cdn-dp";
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
- assigned-clocks = <&cru SCLK_DP_CORE>;
- assigned-clock-rates = <100000000>;
+ assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
+ assigned-clock-rates = <100000000>, <200000000>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
@@ -1234,6 +1236,8 @@
reg = <0x0 0xff650800 0x0 0x40>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -1243,6 +1247,8 @@
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vdec_mmu";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -1252,6 +1258,8 @@
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@@ -1323,7 +1331,9 @@
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
- <&cru ACLK_VIO>;
+ <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
+ <&cru ACLK_GIC_PRE>,
+ <&cru PCLK_DDR>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@@ -1332,7 +1342,9 @@
<100000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>,
- <400000000>;
+ <400000000>, <400000000>,
+ <200000000>,
+ <200000000>;
};
grf: syscon@ff770000 {
@@ -1599,7 +1611,7 @@
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
- clock-names = "aclk", "hclk";
+ clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPL>;
#iommu-cells = <0>;
status = "disabled";
@@ -1656,7 +1668,7 @@
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
- clock-names = "aclk", "hclk";
+ clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPB>;
#iommu-cells = <0>;
status = "disabled";
@@ -1667,6 +1679,8 @@
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";
+ clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
@@ -1677,6 +1691,8 @@
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";
+ clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 15:32:18 +0000