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* arm64: dts: mediatek: mt8186: Add svs nodeRohit Agarwal2024-09-091-0/+16
| | | | | | | | | Add clock/irq/efuse setting in svs nodes for mt8186 SoC. Signed-off-by: Rohit Agarwal <rohiagar@chromium.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240830084544.2898512-4-rohiagar@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add power domain for DPIRohit Agarwal2024-09-091-0/+1
| | | | | | | | | Add power domain phandle to the DPI controller in mediatek mt8186 SoC. Signed-off-by: Rohit Agarwal <rohiagar@chromium.org> Link: https://lore.kernel.org/r/20240830084544.2898512-3-rohiagar@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: add default thermal zonesNicolas Pitre2024-08-061-0/+297
| | | | | | | | | | | Inspired by the vendor kernel but adapted to the upstream thermal driver version. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Pitre <npitre@baylibre.com> Signed-off-by: Julien Panis <jpanis@baylibre.com> Link: https://lore.kernel.org/r/20240603-mtk-thermal-mt818x-dtsi-v7-4-8c8e3c7a3643@baylibre.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: add lvts definitionsNicolas Pitre2024-08-061-0/+19
| | | | | | | | | | | Values extracted from vendor source tree. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> Link: https://lore.kernel.org/r/20240402032729.2736685-8-nico@fluxnic.net [Angelo: Fixed validation and quality issues] Signed-off-by: Julien Panis <jpanis@baylibre.com> Link: https://lore.kernel.org/r/20240603-mtk-thermal-mt818x-dtsi-v7-3-8c8e3c7a3643@baylibre.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: Fix supported-hw mask for GPU OPPsAngeloGioacchino Del Regno2024-07-301-6/+6
| | | | | | | | | | | | | | | | The speedbin eFuse reads a value 'x' from 0 to 7 and, in order to make that compatible with opp-supported-hw, it gets post processed as BIT(x). Change all of the 0x30 supported-hw to 0x20 to avoid getting duplicate OPPs for speedbin 4, and also change all of the 0x8 to 0xcf because speedbins different from 4 and 5 do support 900MHz, 950MHz, 1000MHz with the higher voltage of 850mV, 900mV, 950mV respectively. Fixes: f38ea593ad0d ("arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling") Link: https://lore.kernel.org/r/20240725072243.173104-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllersNícolas F. R. A. Prado2024-02-141-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The mtu3 usb controllers don't list the xhci clock, though they require it, and thus rely on the bootloader leaving it on in order to work. When booting with the upstream arm64 defconfig, the usb controllers will defer probe until modules have loaded since they have an indirect dependency on CONFIG_MTK_CMDQ, which is configured as a module. However at the point where modules are loaded, unused clocks are also disabled, causing the usb controllers to probe without the xhci clock enabled and fail to probe: mtu3 11201000.usb: clks of sts1 are not stable! mtu3 11201000.usb: device enable failed -110 mtu3 11201000.usb: mtu3 hw init failed:-110 mtu3 11201000.usb: failed to initialize gadget mtu3: probe of 11201000.usb failed with error -110 (and same for the one at 11281000) Add the missing clock for the usb controllers so that they can successfully probe without relying on the bootloader state. Fixes: f6c3e61c5486 ("arm64: dts: mediatek: mt8186: Add MTU3 nodes") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240213-mt8186-ssusb-domain-clk-fix-v2-2-1f981d35f3fd@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domainsNícolas F. R. A. Prado2024-02-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The ssusb power domains currently don't list any clocks, despite depending on some, and thus rely on the bootloader leaving the required clocks on in order to work. When booting with the upstream arm64 defconfig, the power domain controller will defer probe until modules have loaded since it has an indirect dependency on CONFIG_MTK_CMDQ, which is configured as a module. However at the point where modules are loaded, unused clocks are also disabled, causing the ssusb domains to fail to be enabled and consequently the controller to fail probe: mtk-power-controller 10006000.syscon:power-controller: /soc/syscon@10006000/power-controller/power-domain@4: failed to power on domain: -110 mtk-power-controller: probe of 10006000.syscon:power-controller failed with error -110 Add the missing clocks for the ssusb power domains so that they can successfully probe without relying on the bootloader state. Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240213-mt8186-ssusb-domain-clk-fix-v2-1-1f981d35f3fd@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: Add video decoder device nodesYunfei Dong2024-02-121-0/+37
| | | | | | | | | | | | Add mt8186 video decoder device nodes. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> [eugen.hristev@collabora.com: minor cleanup] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Link: https://lore.kernel.org/r/20231220133302.39411-1-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: Add jpgenc nodeAllen-KH Cheng2024-02-121-0/+13
| | | | | | | | | | | | | | | Add JPEG encoder node. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Max Staudt <mstaudt@chromium.org> Tested-by: Max Staudt <mstaudt@chromium.org> Reviewed-by: Ricardo Ribalda <ribalda@chromium.org> [eugen.hristev@collabora.com: minor cleanup] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240127084258.68302-2-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: Add venc nodeKyrie Wu2024-02-121-0/+21
| | | | | | | | | | | | | Add video encoder node. Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> [eugen.hristev@collabora.com: minor cleanup] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231228113245.174706-7-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: fix VENC power domain clocksEugen Hristev2024-02-121-1/+1
| | | | | | | | | | | The larb clock is in fact a subsys clock, so it must be prefixed by 'subsys-' to be correctly identified in the driver. Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231228113245.174706-6-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: Add socinfo efuses to MT8173/83/96/92/95 SoCsWilliam-tw Lin2024-02-121-0/+4
| | | | | | | | | | Add efuse nodes for socinfo retrieval for MT8173, MT8183, MT8186, MT8192 and MT8195. Signed-off-by: William-tw Lin <william-tw.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231222080739.21706-2-william-tw.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2024-01-111-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull SoC DT updates from Arnd Bergmann: "There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both the Rockchips rv1109 and Sopgho CV1812H are just minor variations of already supported chips. The other six new SoCs are all part of existing arm64 families, but are somewhat more interesting: - Samsung ExynosAutov920 is an automotive chip, and the first one we support based on the Cortex-A78AE core with lockstep mode. - Google gs101 (Tensor G1) is the chip used in a number of Pixel phones, and is grouped with Samsung Exynos here since it is based on the same SoC design, sharing most of its IP blocks with that series. - MediaTek MT8188 is a new chip used for mid-range tablets and Chromebooks, using two Cortex-A78 cores where the older MT8195 had four of them. - Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range phone SoC and the first supported chip based on Cortex-X4, Cortex-A720 and Cortex-A520. - Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest Laptop chip using the custom Oryon cores. - Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on Cortex-A76 and Cortex-A55 In terms of boards, we have - Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs. - Multiple Rockchips mobile gaming systems (Anbernic RG351V, Powkiddy RK2023, Powkiddy X55) along with the Sonoff iHost Smart Home Hub and a few Rockchips SBCs - Some ComXpress boards based on Marvell CN913x, which is the follow-up to Armada 7xxx/8xxx. - Six new industrial/embedded boards based on NXP i.MX8 and i.MX9 - Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer. - Toradex Verdin AM62 Mallow carrier for TI AM62 - Huashan Pi board based on the SophGo CV1812H RISC-V chip - Two boards based on Allwinner H616/H618 - A number of reference boards for various added SoCs from Qualcomm, Mediatek, Google, Samsung, NXP and Spreadtrum As usual, there are cleanups and warning fixes across all platforms as well as added features for several of them" * tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (857 commits) ARM: dts: usr8200: Fix phy registers arm64: dts: intel: minor whitespace cleanup around '=' arm64: dts: socfpga: agilex: drop redundant status arm64: dts: socfpga: agilex: add unit address to soc node arm64: dts: socfpga: agilex: move firmware out of soc node arm64: dts: socfpga: agilex: move FPGA region out of soc node arm64: dts: socfpga: agilex: align pin-controller name with bindings arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings arm64: dts: socfpga: stratix10: add unit address to soc node arm64: dts: socfpga: stratix10: move firmware out of soc node arm64: dts: socfpga: stratix10: move FPGA region out of soc node arm64: dts: socfpga: stratix10: align pincfg nodes with bindings arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size ARM: dts: socfpga: align NAND controller name with bindings ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size arm64: dts: rockchip: Fix led pinctrl of lubancat 1 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6 arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b ...
| * arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxesEugen Hristev2023-12-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix warnings reported by dtbs_check : arch/arm64/boot/dts/mediatek/mt8186.dtsi:1163.35-1168.5: Warning (simple_bus_reg): /soc/mailbox@10686000: simple-bus unit address format error, expected "10686100" arch/arm64/boot/dts/mediatek/mt8186.dtsi:1170.35-1175.5: Warning (simple_bus_reg): /soc/mailbox@10687000: simple-bus unit address format error, expected "10687100" by having the right bus address as node name. Fixes: 379cf0e639ae ("arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Link: https://lore.kernel.org/r/20231204135533.21327-1-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
| * arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0Chen-Yu Tsai2023-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | The alias prefix for ovl_2l (2 layer overlay) is "ovl-2l", not "ovl_2l". Fix this. Fixes: 7e07d3322de2 ("arm64: dts: mediatek: mt8186: Add display nodes") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20231130074032.913511-4-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* | arm64: dts: mediatek: mt8186: fix clock names for power domainsEugen Hristev2023-11-291-15/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clocks for each power domain are split into big categories: pd clocks and subsys clocks. According to the binding, all clocks which have a dash '-' in their name are treated as subsys clocks, and must be placed at the end of the list. The other clocks which are pd clocks must come first. Fixed the naming and the placing of all clocks in the power domains. For the avoidance of doubt, prefixed all subsys clocks with the 'subsys' prefix. The binding does not enforce strict clock names, the driver uses them in bulk, only making a difference for pd clocks vs subsys clocks. The above problem appears to be trivial, however, it leads to incorrect power up and power down sequence of the power domains, because some clocks will be mistakenly taken for subsys clocks and viceversa. One consequence is the fact that if the DIS power domain goes power down and power back up during the boot process, when it comes back up, there are still transactions left on the bus which makes the display inoperable. Some of the clocks for the DIS power domain were wrongly using '_' instead of '-', which again made these clocks being treated as pd clocks instead of subsys clocks. Cc: stable@vger.kernel.org Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20231005103041.352478-1-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* | arm64: dts: mediatek: mt8186: Change gpu speedbin nvmem cell nameAngeloGioacchino Del Regno2023-11-291-1/+1
|/ | | | | | | | | | | | | | MT8186's GPU speedbin value must be interpreted, or the value will not be meaningful. Use the correct "gpu-speedbin" nvmem cell name for the GPU speedbin to allow triggering the cell info fixup handler, hence feeding the right speedbin number to the users. Cc: stable@vger.kernel.org Fixes: 263d2fd02afc ("arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells") Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20231005151150.355536-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
* arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scalingChen-Yu Tsai2023-06-151-1/+139
| | | | | | | | | | | | | | Add the GPU's OPP table. This is from the downstream ChromeOS kernel, adapted to the new upstream opp-supported-hw binning format. Also add dynamic-power-coefficient for the GPU. Also add label for mfg1 power domain. This is to be used at the board level to add a regulator supply for the power domain. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-5-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cellsChen-Yu Tsai2023-06-151-0/+7
| | | | | | | | | | | | On the MT8186, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse. Add the NVMEM cell, and tie it to the GPU. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-4-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scalingChen-Yu Tsai2023-06-151-0/+242
| | | | | | | | | | | This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for CPU freqency and voltage scaling is available. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-3-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP tableChen-Yu Tsai2023-06-151-0/+101
| | | | | | | | | | | Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-2-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: add missing cache propertiesKrzysztof Kozlowski2023-05-291-0/+2
| | | | | | | | | | | As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230421223157.115367-1-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add display nodesAllen-KH Cheng2023-05-291-0/+116
| | | | | | | | | | | Add display nodes and the GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add GCE nodeAllen-KH Cheng2023-05-291-0/+10
| | | | | | | | | Add the Global Command Engine (GCE) node for MT8186 SoC Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add ADSP nodeAllen-KH Cheng2023-05-291-0/+16
| | | | | | | | | Add ADSP node for MT8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add SPMI nodeAllen-KH Cheng2023-05-291-0/+15
| | | | | | | | | Add SPMI node for MT8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add MTU3 nodesAllen-KH Cheng2023-05-291-0/+68
| | | | | | | | | | Add MTU3 nodes for MT8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* Merge tag 'iommu-updates-v6.4' of ↵Linus Torvalds2023-04-301-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: - Convert to platform remove callback returning void - Extend changing default domain to normal group - Intel VT-d updates: - Remove VT-d virtual command interface and IOASID - Allow the VT-d driver to support non-PRI IOPF - Remove PASID supervisor request support - Various small and misc cleanups - ARM SMMU updates: - Device-tree binding updates: * Allow Qualcomm GPU SMMUs to accept relevant clock properties * Document Qualcomm 8550 SoC as implementing an MMU-500 * Favour new "qcom,smmu-500" binding for Adreno SMMUs - Fix S2CR quirk detection on non-architectural Qualcomm SMMU implementations - Acknowledge SMMUv3 PRI queue overflow when consuming events - Document (in a comment) why ATS is disabled for bypass streams - AMD IOMMU updates: - 5-level page-table support - NUMA awareness for memory allocations - Unisoc driver: Support for reattaching an existing domain - Rockchip driver: Add missing set_platform_dma_ops callback - Mediatek driver: Adjust the dma-ranges - Various other small fixes and cleanups * tag 'iommu-updates-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (82 commits) iommu: Remove iommu_group_get_by_id() iommu: Make iommu_release_device() static iommu/vt-d: Remove BUG_ON in dmar_insert_dev_scope() iommu/vt-d: Remove a useless BUG_ON(dev->is_virtfn) iommu/vt-d: Remove BUG_ON in map/unmap() iommu/vt-d: Remove BUG_ON when domain->pgd is NULL iommu/vt-d: Remove BUG_ON in handling iotlb cache invalidation iommu/vt-d: Remove BUG_ON on checking valid pfn range iommu/vt-d: Make size of operands same in bitwise operations iommu/vt-d: Remove PASID supervisor request support iommu/vt-d: Use non-privileged mode for all PASIDs iommu/vt-d: Remove extern from function prototypes iommu/vt-d: Do not use GFP_ATOMIC when not needed iommu/vt-d: Remove unnecessary checks in iopf disabling path iommu/vt-d: Move PRI handling to IOPF feature path iommu/vt-d: Move pfsid and ats_qdep calculation to device probe path iommu/vt-d: Move iopf code from SVA to IOPF enabling path iommu/vt-d: Allow SVA with device-specific IOPF dmaengine: idxd: Add enable/disable device IOPF feature arm64: dts: mt8186: Add dma-ranges for the parent "soc" node ...
| * arm64: dts: mt8186: Add dma-ranges for the parent "soc" nodeYong Wu2023-04-131-0/+1
| | | | | | | | | | | | | | | | | | Prepare for the MM nodes whose dma-ranges(iova range) is 16GB. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230411093144.2690-15-yong.wu@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
* | arm64: dts: mediatek: mt8186: Add GPU nodeAngeloGioacchino Del Regno2023-03-301-0/+17
|/ | | | | | | | | | Add a GPU node for MT8186 SoC but keep it disabled. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Fix watchdog compatibleAngeloGioacchino Del Regno2023-02-011-2/+1
| | | | | | | | | | | | | | MT8186's watchdog embeds a reset controller and needs only the mediatek,mt8186-wdt compatible string as the MT6589 one is there for watchdogs that don't have any reset controller capability. Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Co-developed-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20221108033209.22751-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mt8186: Change idle states names to reflect actual functionAngeloGioacchino Del Regno2023-01-311-12/+12
| | | | | | | | | | | | | | | | | The names of the idle states are misleading being this a single cluster SoC, a cluster-off idle state is impossible! After some research in ATF, it emerged that the cpu-off state is in reality putting CPUs in retention state, while the cluster-off one is turning off the CPUs. Summarizing renaming: - cpu-off -> cpu-retention - cluster-off -> cpu-off Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230126103526.417039-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mt8186: Fix CPU map for single-cluster SoCAngeloGioacchino Del Regno2023-01-311-4/+2
| | | | | | | | | | | MT8186 features the ARM DynamIQ technology and combines both two Cortex-A76 (big) and six Cortex-A55 (LITTLE) CPUs in one cluster: fix the CPU map to reflect that. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Link: https://lore.kernel.org/r/20230126103526.417039-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add DPI nodeAllen-KH Cheng2023-01-191-0/+17
| | | | | | | | | | Add DPI node for MT8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118091829.755-8-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add audio controller nodeAllen-KH Cheng2023-01-191-0/+62
| | | | | | | | | Add audio controller node for MT8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118091829.755-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add ADSP mailbox nodesAllen-KH Cheng2023-01-191-0/+14
| | | | | | | | | Add ADSP mailbox node for MT8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118091829.755-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Add crypto support for eMMC controllerAllen-KH Cheng2023-01-091-3/+4
| | | | | | | | | For crypto support, add a crypto clock of the inline crypto engine and expand the register size in the eMMC controller. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Link: https://lore.kernel.org/r/20221221104856.28770-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mt8186: Add complete CPU caches informationAngeloGioacchino Del Regno2023-01-091-0/+58
| | | | | | | | | | | | | | | | | | This SoC features two clusters composed of: - 6x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 2x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 1MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221206112330.78431-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mediatek: mt8186: Fix systimer 13 MHz clock descriptionChen-Yu Tsai2023-01-091-3/+5
| | | | | | | | | | | | | | | The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally. The 13 MHz clock is not a separate oscillator. Fix this by making the 13 MHz clock a divide-by-2 fixed factor clock, taking its input from the main 26 MHz oscillator. Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221201084229.3464449-5-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mt8186: Add dsi nodeAllen-KH Cheng2023-01-091-0/+19
| | | | | | | | Add dsi node for mt8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Link: https://lore.kernel.org/r/20221123135531.23221-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mt8186: Add IOMMU and SMI nodesAllen-KH Cheng2023-01-091-0/+173
| | | | | | | | Add iommu and smi nodes for mt8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Link: https://lore.kernel.org/r/20221123135531.23221-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: mt8186: Add power domains controllerAllen-KH Cheng2023-01-091-0/+188
| | | | | | | | Add power domains controller for mt8186 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Link: https://lore.kernel.org/r/20221123135531.23221-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: Update cache properties for mediatekPierre Gondois2022-11-081-0/+3
| | | | | | | | | | | | | | The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20221107155825.1644604-13-pierre.gondois@arm.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
* arm64: dts: Add MediaTek MT8186 dts and evaluation board and MakefileAllen-KH Cheng2022-08-291-0/+819
MT8186 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55 and 2 CA76 cores. MT8186 share many HW IP with MT65xx series. We add basic chip support for MediaTek MT8186 on evaluation board. Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> Link: https://lore.kernel.org/r/20220825170448.17024-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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