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path: root/arch/riscv/kernel/traps.c
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* Merge patch "drivers: perf: Do not broadcast to other cpus when starting a co...Palmer Dabbelt2023-11-091-10/+18
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| * riscv: Only consider swbp/ss handlers for correct privileged modeBjörn Töpel2023-09-201-10/+18
* | riscv: add userland instruction dump to RISC-V splatsYunhui Cui2023-11-051-3/+18
* | Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-051-9/+0
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| * | riscv: add support for misaligned trap handling in S-modeClément Léger2023-11-011-9/+0
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* | riscv: Deduplicate IRQ stack switchingSami Tolvanen2023-10-271-28/+4
* | riscv: VMAP_STACK overflow detection thread-safeDeepak Gupta2023-10-271-35/+1
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* Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-09-011-1/+3
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| * riscv: Add CFI error handlingSami Tolvanen2023-08-231-1/+3
* | riscv: stack: Fixup independent irq stack for CONFIG_FRAME_POINTER=nGuo Ren2023-08-161-0/+3
* | riscv: entry: set a0 = -ENOSYS only when syscall != -1Celeste Liu2023-08-161-3/+3
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* riscv: Discard vector state on syscallsBjörn Töpel2023-07-041-0/+2
* riscv: vector: only enable interrupts in the first-use trapAndy Chiu2023-07-011-1/+7
* riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACKGuo Ren2023-06-221-2/+33
* riscv: Allocate user's vector context in the first-use trapAndy Chiu2023-06-081-2/+24
* riscv: entry: Save a0 prior syscall_enter_from_user_mode()Björn Töpel2023-04-111-2/+2
* riscv: entry: Convert to generic entryGuo Ren2023-03-231-18/+122
* riscv: entry: Add noinstr to prevent instrumentation insertedGuo Ren2023-03-231-2/+2
* Merge patch series "riscv: Dump faulting instructions in oops handler"Palmer Dabbelt2023-02-211-1/+24
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| * riscv: Add instruction dump to RISC-V splatsBjörn Töpel2023-02-211-1/+24
* | riscv: Avoid enabling interrupts in die()Mattias Nissler2023-02-211-2/+3
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* Merge patch series "RISC-V: Align the shadow stack"Palmer Dabbelt2022-12-121-3/+27
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| * RISC-V: Add some comments about the shadow and overflow stacksPalmer Dabbelt2022-12-121-7/+13
| * RISC-V: Align the shadow stackPalmer Dabbelt2022-12-121-1/+1
| * riscv: fix race when vmap stack overflowJisheng Zhang2022-11-291-0/+18
* | RISC-V: Avoid dereferening NULL regs in die()Palmer Dabbelt2022-10-121-3/+6
* | riscv: traps: add missing prototypeConor Dooley2022-08-181-1/+2
* | RISC-V: Add fast call path of crash_kexec()Xianting Tian2022-07-211-0/+4
* | riscv: integrate alternatives better into the main architectureHeiko Stuebner2022-05-111-1/+1
* | exit: Add and use make_task_dead.Eric W. Biederman2021-12-131-1/+1
* | trap: cleanup trap_init()Kefeng Wang2021-09-081-5/+0
* | Merge tag 'riscv-for-linus-5.14-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-07-091-0/+35
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| * riscv: add VMAP_STACK overflow detectionTong Tiangen2021-07-061-0/+35
* | riscv: xip: support runtime trap patchingVitaly Wool2021-06-101-4/+9
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* riscv: remove unused handle_exception symbolRouven Czerwinski2021-05-061-2/+0
* Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2021-05-061-1/+1
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| * riscv: add __init section marker to some functionsJisheng Zhang2021-04-261-1/+1
* | riscv: add do_page_fault and do_trap_break into the kprobes blacklistJisheng Zhang2021-04-151-0/+1
* | riscv: traps: Fix no prototype warningsNanyong Sun2021-03-091-0/+1
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* riscv: Add dump stack in show_regsKefeng Wang2021-01-141-1/+2
* riscv: Add uprobes supportedGuo Ren2021-01-141-0/+10
* riscv: Add kprobes supportedGuo Ren2021-01-141-0/+9
* RISC-V: Setup exception vector earlyAtish Patra2020-07-301-7/+1
* maccess: rename probe_kernel_address to get_kernel_nofaultChristoph Hellwig2020-06-181-2/+2
* irqchip: RISC-V per-HART local interrupt controller driverAnup Patel2020-06-091-2/+0
* riscv: Add KGDB supportVincent Chen2020-05-181-0/+5
* Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2020-04-091-5/+27
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| * riscv: Unaligned load/store handling for M_MODEDamien Le Moal2020-04-031-3/+24
| * RISC-V: Add supported for ordered booting method using HSMAtish Patra2020-03-311-1/+1
| * riscv: add macro to get instruction lengthZong Li2020-03-261-1/+2
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