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* Revert "MIPS: Add basic support for ptrace single step"Thomas Bogendoerfer2021-02-184-116/+1
| | | | | | | | | | This reverts commit 7c86ff9925cbc83e8a21f164a8fdc2767e03531e. There are too many special cases for MIPS not covered by this patch. In the end it might be better to implement single stepping in userland than emulating it in the kernel. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: kernel: Drop kgdb_call_nmi_hookThomas Bogendoerfer2021-02-151-5/+0
| | | | | | | With the removal of set_fs() calls kgdb_call_nmi_hook() is now the same as the default implementation, so we can remove it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Use common way to parse elfcorehdrJinyang He2021-02-131-28/+21
| | | | | | | "elfcorehdr" can be parsed at kernel/crash_dump.c Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Simplify EVA cache handlingThomas Bogendoerfer2021-02-131-56/+11
| | | | | | | | protected_cache_op is only used for flushing user addresses, so we only need to define protected_cache_op different in EVA mode and be done with it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* Revert "MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache ↵Thomas Bogendoerfer2021-02-132-21/+1
| | | | | | | | | | | | | flushes" This reverts commit 6ebda44f366478d1eea180d93154e7d97b591f50. All icache flushes in this code paths are done via flush_icache_range(), which only uses normal cache instruction. And this is the correct thing for EVA mode, too. So no need to do set_fs(KERNEL_DS) here. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Christoph Hellwig <hch@lst.de>
* MIPS: remove CONFIG_DMA_PERDEV_COHERENTChristoph Hellwig2021-02-132-2/+3
| | | | | | | | | Just select DMA_NONCOHERENT and ARCH_HAS_SETUP_DMA_OPS from the MIPS_GENERIC platform instead. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: remove CONFIG_DMA_MAYBE_COHERENTChristoph Hellwig2021-02-132-7/+3
| | | | | | | | CONFIG_DMA_MAYBE_COHERENT just guards two early init options now. Just enable them unconditionally for CONFIG_DMA_NONCOHERENT. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* driver core: lift dma_default_coherent into common codeChristoph Hellwig2021-02-139-33/+4
| | | | | | | | | | | | | Lift the dma_default_coherent variable from the mips architecture code to the driver core. This allows an architecture to sdefault all device to be DMA coherent at run time, even if the kernel is build with support for DMA noncoherent device. By allowing device_initialize to set the ->dma_coherent field to this default the amount of arch hooks required for this behavior can be greatly reduced. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: refactor the runtime coherent vs noncoherent DMA indicatorsChristoph Hellwig2021-02-136-40/+16
| | | | | | | | Replace the global coherentio enum, and the hw_coherentio (fake) boolean variables with a single boolean dma_default_coherent flag. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS/alchemy: factor out the DMA coherent setupChristoph Hellwig2021-02-131-14/+19
| | | | | | | | | Factor out a alchemy_dma_coherent helper that determines if the platform is DMA coherent. Also stop initializing the hw_coherentio variable, given that is only ever set to a non-zero value by the malta setup code. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS/malta: simplify plat_setup_iocoherencyChristoph Hellwig2021-02-131-23/+9
| | | | | | | | | | | Given that plat_mem_setup runs before earlyparams are handled and malta selects CONFIG_DMA_MAYBE_COHERENT, coherentio can only be set to IO_COHERENCE_DEFAULT at this point. So remove the checking for other options and merge plat_enable_iocoherency into plat_setup_iocoherency to simplify the code a bit. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Add basic support for ptrace single stepTiezhu Yang2021-02-134-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current code, arch_has_single_step() is not defined on MIPS, that means MIPS does not support instruction single-step for user mode. Delve is a debugger for the Go programming language, the ptrace syscall PtraceSingleStep() failed [1] on MIPS and then the single step function can not work well, we can see that PtraceSingleStep() definition returns ptrace(PTRACE_SINGLESTEP) [2]. So it is necessary to support ptrace single step on MIPS. At the beginning, we try to use the Debug Single Step exception on the Loongson 3A4000 platform, but it has no effect when set CP0_DEBUG SSt bit, this is because CP0_DEBUG NoSSt bit is 1 which indicates no single-step feature available [3], so this way which is dependent on the hardware is almost impossible. With further research, we find out there exists a common way used with break instruction in arch/alpha/kernel/ptrace.c, it is workable. For the above analysis, define arch_has_single_step(), add the common function user_enable_single_step() and user_disable_single_step(), set flag TIF_SINGLESTEP for child process, use break instruction to set breakpoint. We can use the following testcase to test it: tools/testing/selftests/breakpoints/step_after_suspend_test.c $ make -C tools/testing/selftests TARGETS=breakpoints $ cd tools/testing/selftests/breakpoints Without this patch: $ ./step_after_suspend_test -n TAP version 13 1..4 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 1 # SKIP CPU 0 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 2 # SKIP CPU 1 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 3 # SKIP CPU 2 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 4 # SKIP CPU 3 # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:4 error:0 With this patch: $ ./step_after_suspend_test -n TAP version 13 1..4 ok 1 CPU 0 ok 2 CPU 1 ok 3 CPU 2 ok 4 CPU 3 # Totals: pass:4 fail:0 xfail:0 xpass:0 skip:0 error:0 [1] https://github.com/go-delve/delve/blob/master/pkg/proc/native/threads_linux.go#L50 [2] https://github.com/go-delve/delve/blob/master/vendor/golang.org/x/sys/unix/syscall_linux.go#L1573 [3] http://www.t-es-t.hu/download/mips/md00047f.pdf Reported-by: Guoqi Chen <chenguoqi@loongson.cn> Signed-off-by: Xingxing Su <suxingxing@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Make check condition for SDBBP consistent with EJTAG specTiezhu Yang2021-02-112-2/+6
| | | | | | | | | | | | | | | | According to MIPS EJTAG Specification [1], a Debug Breakpoint exception occurs when an SDBBP instruction is executed, the CP0_DEBUG bit DBp indicates that a Debug Breakpoint exception occurred. When I read the original code, it looks a little confusing at first glance, just check bit DBp for SDBBP to make the code more readable, it will be much easier to understand. [1] http://www.t-es-t.hu/download/mips/md00047f.pdf Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* mips: Replace lkml.org links with loreKees Cook2021-02-111-6/+5
| | | | | | | | | As started by commit 05a5f51ca566 ("Documentation: Replace lkml.org links with lore"), replace lkml.org links with lore to better use a single source that's more likely to stay available long-term. Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* Revert "MIPS: microMIPS: Fix the judgment of mm_jr16_op and mm_jalr_op"Thomas Bogendoerfer2021-02-091-3/+3
| | | | | | This reverts commit 9308579fef3ddde19da9d45e23bf36d41932417f. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: crash_dump.c: Simplify copy_oldmem_page()Youling Tang2021-02-091-35/+6
| | | | | | | | | | | | | Replace kmap_atomic_pfn() with kmap_local_pfn() which is preemptible and can take page faults. Remove the indirection of the dump page and the related cruft which is not longer required. Remove unused or redundant header files. Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* Revert "mips: Manually call fdt_init_reserved_mem() method"Serge Semin2021-02-091-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 3751cbda8f223549d7ea28803cbec8ac87e43ed2. Originally the patch was created to fix the reserved-memory DT-node parsing failure on the early stages of the platform memory initialization. That happened due to the two early memory allocators utilization that time: bootmem and memblock. At first the platform-specific memory mapping array was initialized. Then the early_init_fdt_scan_reserved_mem() was called, which couldn't fully parse the "reserved-memory" DT-node since neither memblock nor bootmem allocators hadn't been initialized at that stage, so the fdt_init_reserved_mem() method failed on the memory allocation calls. Only after that the platform-specific memory mapping were used to create proper bootmem and memblock structures and let the early memory allocations work. That's why we had to call the fdt_init_reserved_mem() method one more time to retry the initialization of the features like CMA. The necessity to have that fix was disappeared after the full memblock support had been added to the MIPS kernel and all plat_mem_setup() had been fixed to add the memory regions right into the memblock memory pool. Let's revert that patch then especially after having Paul reported that the second fdt_init_reserved_mem() call causes the reserved memory pool being created twice bigger than implied. Fixes: a94e4f24ec83 ("MIPS: init: Drop boot_mem_map") Reported-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: process: Fix no previous prototype warningJinyang He2021-02-091-0/+2
| | | | | | | | | | unwind_stack_by_address and unwind_stack need <asm/stacktrace.h>. arch_align_stack needs <asm/exec.h> link: https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org/thread/ZPL2RRA6RZKRQZI5IGOVLFXN2GVZBN3L/ Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: compressed: fix build with enabled UBSANAlexander Lobakin2021-02-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1e35918ad9d1 ("MIPS: Enable Undefined Behavior Sanitizer UBSAN") added a possibility to build the entire kernel with UBSAN instrumentation for MIPS, with the exception for VDSO. However, self-extracting head wasn't been added to exceptions, so this occurs: mips-alpine-linux-musl-ld: arch/mips/boot/compressed/decompress.o: in function `FSE_buildDTable_wksp': decompress.c:(.text.FSE_buildDTable_wksp+0x278): undefined reference to `__ubsan_handle_shift_out_of_bounds' mips-alpine-linux-musl-ld: decompress.c:(.text.FSE_buildDTable_wksp+0x2a8): undefined reference to `__ubsan_handle_shift_out_of_bounds' mips-alpine-linux-musl-ld: decompress.c:(.text.FSE_buildDTable_wksp+0x2c4): undefined reference to `__ubsan_handle_shift_out_of_bounds' mips-alpine-linux-musl-ld: arch/mips/boot/compressed/decompress.o: decompress.c:(.text.FSE_buildDTable_raw+0x9c): more undefined references to `__ubsan_handle_shift_out_of_bounds' follow Add UBSAN_SANITIZE := n to mips/boot/compressed/Makefile to exclude it from instrumentation scope and fix this issue. Fixes: 1e35918ad9d1 ("MIPS: Enable Undefined Behavior Sanitizer UBSAN") Cc: stable@vger.kernel.org # 5.0+ Signed-off-by: Alexander Lobakin <alobakin@pm.me> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: relocatable: Use __kaslr_offset in show_kernel_relocationJinyang He2021-02-091-6/+2
| | | | | | | | | The type of the VMLINUX_LOAD_ADDRESS macro is the (unsigned long long) in 32bits kernel but (unsigned long) in the 64-bit kernel. Although there is no error here, avoid using it to calculate kaslr_offset. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: relocatable: Provide kaslr_offset() to get the kernel offsetJinyang He2021-02-093-0/+19
| | | | | | | | | | | Provide kaslr_offset() to get the kernel offset when KASLR is enabled. Error may occur before update_kaslr_offset(), so put it at the end of the offset branch. Fixes: a307a4ce9ecd ("MIPS: Loongson64: Add KASLR support") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: kernel: Support extracting off-line stack traces from user-space with perfTiezhu Yang2021-02-044-1/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | Add perf_event_mips_regs/perf_reg_value/perf_reg_validate to support features HAVE_PERF_REGS/HAVE_PERF_USER_STACK_DUMP in kernel. [ayan@wavecomp.com: Repick this patch for unwinding userstack backtrace by perf and libunwind on MIPS based CPU.] [ralf@linux-mips.org: Add perf_get_regs_user() which is required after 'commit 88a7c26af8da ("perf: Move task_pt_regs sampling into arch code")'.] [yangtiezhu@loongson.cn: Fix build error about perf_get_regs_user() after commit 76a4efa80900 ("perf/arch: Remove perf_sample_data::regs_user_copy"), and also separate the original patches into two parts (MIPS kernel and perf tools) to merge easily.] The original patches: https://lore.kernel.org/patchwork/patch/1126521/ https://lore.kernel.org/patchwork/patch/1126520/ Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Archer Yan <ayan@wavecomp.com> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: pistachio: remove obsolete include/asm/mach-pistachioAlexander Lobakin2021-02-042-17/+0
| | | | | | | | | | Since commit 02bd530f888c ("MIPS: generic: Increase NR_IRQS to 256") include/asm/mach-pistachio/irq.h just does nothing. Remove the file along with mach-pistachio folder and include compiler directive. Signed-off-by: Alexander Lobakin <alobakin@pm.me> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* mips: dts: Add support for Cisco SG220-26 switchBert Vermeulen2021-02-042-0/+27
| | | | | Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Add Realtek RTL838x/RTL839x support as generic MIPS systemBert Vermeulen2021-02-041-0/+21
| | | | | | | | This is just enough system to boot the kernel with earlycon working. Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* Add support for Realtek RTL838x/RTL839x switch SoCsBert Vermeulen2021-02-043-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTL838x/839x family of SoCs are Realtek switches with an embedded MIPS core. * RTL838x - 500MHz 4kce single core - 1Gbit ports and L2 features * RTL839x - 700MHz 34Kc single core - 1Gbit ports and L2 features These switches, depending on the exact part number, will have anywhere between 8 and 52 ports. The MIPS core is wired to a switch cpu port which has a tagging feature allowing us to make use of the DSA subsystem. The SoCs are somewhat basic in certain areas, getting better with more advanced features on newer series. The switch functionality is MMIO-mapped via a large MFD region. The SoCs have the following peripherals * ethernet * switch * uart - ns16550a * spi-flash interface * gpio * wdt * led The code was derived from various vendor SDKs based on Linux v2.6 kernels. This patchset allows us to boot RTL838x/RTL839x units with basic support. Most of the other drivers are already written and functional, and work to get them upstream is already in progress. Signed-off-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: ralink: manage low reset linesSander Vanheule2021-02-041-2/+2
| | | | | | | | | | | | | | | | | | | Reset lines with indices smaller than 8 are currently considered invalid by the rt2880-reset reset controller. The MT7621 SoC uses a number of these low reset lines. The DTS defines reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2. As a result of the above restriction, these resets cannot be asserted or de-asserted by the reset controller. In cases where the bootloader does not de-assert these lines, this results in e.g. the MT7621's internal switch staying in reset. Change the reset controller to only ignore the system reset, so all reset lines with index greater than 0 are considered valid. Signed-off-by: Sander Vanheule <sander@svanheule.net> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: of: Introduce helper function to get DTBThomas Bogendoerfer2021-02-0410-77/+39
| | | | | | | | | Selection of the DTB to be used was burried in more or less readable code in head.S. Move this code into a inline helper function and use it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
* arch: mips: kernel: Fix two spelling in smp.cBhaskar Chowdhury2021-02-031-3/+3
| | | | | | | | | s/logcal/logical/ s/intercpu/inter-CPU/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: malta-time: remove unneeded semicolonYang Li2021-02-031-1/+1
| | | | | | | | | Eliminate the following coccicheck warning: ./arch/mips/mti-malta/malta-time.c:141:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* KVM: MIPS: remove unneeded semicolonYang Li2021-02-031-1/+1
| | | | | | | | | | Eliminate the following coccicheck warning: ./arch/mips/kvm/mips.c:151:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: fix kernel_stack_pointer()Huang Pei2021-02-031-1/+1
| | | | | | | MIPS always save kernel stack pointer in regs[29] Signed-off-by: Huang Pei <huangpei@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Fix inline asm input/output type mismatch in checksum.h used with ClangTiezhu Yang2021-01-271-2/+4
| | | | | | | | | | | | | | | | | | | | | | | Fix the following build error when make M=samples/bpf used with Clang: CLANG-bpf samples/bpf/sockex2_kern.o In file included from samples/bpf/sockex2_kern.c:7: In file included from ./include/uapi/linux/if_tunnel.h:7: In file included from ./include/linux/ip.h:16: In file included from ./include/linux/skbuff.h:28: In file included from ./include/net/checksum.h:22: ./arch/mips/include/asm/checksum.h:161:9: error: unsupported inline asm: input with type 'unsigned long' matching output with type '__wsum' (aka 'unsigned int') : "0" ((__force unsigned long)daddr), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. This is a known issue on MIPS [1], the changed code can be compiled successfully by both GCC and Clang. [1] https://lore.kernel.org/linux-mips/CAG_fn=W0JHf8QyUX==+rQMp8PoULHrsQCa9Htffws31ga8k-iw@mail.gmail.com/ Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mm:remove function __uncached_access()Yanteng Si2021-01-271-8/+0
| | | | | | | | MIPS can now use the default uncached_access like other archs. Signed-off-by: Yanteng Si <siyanteng@loongson.cn> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: loongson2ef: remove function __uncached_access()Yanteng Si2021-01-271-11/+0
| | | | | | | We no longer need the MESA workaround, so remove it. Signed-off-by: Yanteng Si <siyanteng@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: asm: spram: remove unneeded semicolonChengyang Fan2021-01-271-1/+1
| | | | | | | Remove a superfluous semicolon after function definition. Signed-off-by: Chengyang Fan <cy.fan@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: vpe: Remove vpe_getcwdThomas Bogendoerfer2021-01-272-36/+0
| | | | | | | I couldn't find any user of the dubious vpe_getcwd so far. So remove it and get rid of another set_fs(KERNEL_DS). Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* mips: cacheinfo: Remove unnecessary increment of levelSouptick Joarder2021-01-271-3/+1
| | | | | | | | | | | | | | kernel test robot throws below warning -> arch/mips/kernel/cacheinfo.c:112:3: warning: Variable 'level' is modified but its new value is never used. [unreadVariable] Remove unnecessary increment of level at the end. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Add is_jr_ra_ins() to end the loop earlyJinyang He2021-01-251-1/+33
| | | | | | | | | | | | | | | | | | | | | For those leaf functions, they are likely to have no stack operations. Add is_jr_ra_ins() to determine whether jr ra has been touched before the frame_size is found. Without this patch, the get frame_size operation may be out of range and get the frame_size from the next nested function. There is no POOL32A format in uapi/asm/inst.h, so some bits here use the format of r_format instead. e.g. --------------------------------------------------------------------- | format | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 | -----------------+---------+-------+-------+------------+------------ | pool32a_format | pool32a | rt | rs | jalrc | pool32axf | -----------------+---------+-------+-------+------------+------------ | r_format | opcode | rs | rt | rd:5, re:5 | func | --------------------------------------------------------------------- Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Fix get_frame_info() handing of function sizeJinyang He2021-01-251-4/+4
| | | | | | | | | | | | | | | | | | | [1]: Commit b6c7a324df37b ("MIPS: Fix get_frame_info() handling of microMIPS function size") [2]: Commit 2b424cfc69728 ("MIPS: Remove function size check in get_frame_info()") First patch added a constant to check the number of iterations against. Second patch fixed the situation that info->func_size is zero. However, func_size member became useless after the second commit. Without ip_end, the get frame_size operation may be out of range although KALLSYMS enabled. Thus, check func_size first. Then make ip_end be the sum of ip and a constant (512) if func_size is equal to 0. Otherwise make ip_end be the sum of ip and func_size. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: microMIPS: Fix the judgment of mm_jr16_op and mm_jalr_opJinyang He2021-01-251-3/+3
| | | | | | | | | | | | mm16_r5_format.rt is 5 bits, so directly judge the value if equal or not. mm_jalr_op requires 7th to 16th bits. These 10 which bits generated by shifting u_format.uimmediate by 6 may be affected by sign extension. Thus, take out the 10 bits for comparison. Without this patch, errors may occur, such as these bits are all ones. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: process: Remove unnecessary headers inclusionJinyang He2021-01-251-29/+12
| | | | | | | | Some headers are not necessary, remove them and sort includes. Signed-off-by: Jinyang He <hejinyang@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: make kgdb depend on FPU supportArnd Bergmann2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | kgdb fails to build when the FPU support is disabled: arch/mips/kernel/kgdb.c: In function 'dbg_set_reg': arch/mips/kernel/kgdb.c:147:35: error: 'struct thread_struct' has no member named 'fpu' 147 | memcpy((void *)&current->thread.fpu.fcr31, mem, | ^ arch/mips/kernel/kgdb.c:155:34: error: 'struct thread_struct' has no member named 'fpu' 155 | memcpy((void *)&current->thread.fpu.fpr[fp_reg], mem, This is only relevant for CONFIG_EXPERT=y, so disallowing it in Kconfig is an easier workaround than fixing it properly. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: jazz: always allow little-endian buildsArnd Bergmann2021-01-222-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel test robot keeps reporting the same bug when it shows up in new files after random unrelated patches: In file included from arch/mips/include/uapi/asm/byteorder.h:13, from arch/mips/include/asm/bitops.h:20, from include/linux/bitops.h:26, from include/linux/kernel.h:12, from include/linux/clk.h:13, from drivers/base/regmap/regmap-mmio.c:7: include/linux/byteorder/big_endian.h:8:2: warning: #warning inconsistent configuration, needs CONFIG_CPU_BIG_ENDIAN [-Wcpp] 8 | #warning inconsistent configuration, needs CONFIG_CPU_BIG_ENDIAN | ^~~~~~~ drivers/base/regmap/regmap-mmio.c: In function 'regmap_mmio_gen_context': >> drivers/base/regmap/regmap-mmio.c:274:2: error: duplicate case value 274 | case REGMAP_ENDIAN_NATIVE: | ^~~~ drivers/base/regmap/regmap-mmio.c:246:2: note: previously used here 246 | case REGMAP_ENDIAN_NATIVE: The problem is that some randconfig builds end up on the MIPS jazz platform with neither CONFIG_CPU_BIG_ENDIAN nor CONFIG_CPU_LITTLE_ENDIAN because no specific machine is selected. As it turns out, all jazz machines support little-endian kernels, so this can simply be allowed globally. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: Make definitions of MIPSInst_FMA_{FUNC,FMTM} consistent with MIPS64 manualTiezhu Yang2021-01-221-3/+3
| | | | | | | | | | | | | The kernel definitions of MIPSInst_FMA_FUNC and MIPSInst_FMA_FFMT are not consistent with MADD.fmt, NMADD.fmt and NMSUB.fmt in the MIPS64 manual [1], the field func is bit 5..3 and fmt is bit 2..0, fix them. Otherwise there exists error when add new instruction simulation. [1] https://www.mips.com/?do-download=the-mips64-instruction-set-v6-06 Reported-by: Ming Wang <wangming01@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* mips: Add N64 machine typeLauri Kasanen2021-01-228-0/+223
| | | | | | | Add support for the Nintendo 64. Signed-off-by: Lauri Kasanen <cand@gmx.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* Revert "MIPS: Remove unused R4300 CPU support"Lauri Kasanen2021-01-229-1/+33
| | | | | | | | | This reverts commit f9065b54d437c4660e3d974ad9ce5188c068cd76. We're adding Nintendo 64 support, so the VR4300 is no longer unused. Signed-off-by: Lauri Kasanen <cand@gmx.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mm: Add prototype for function __update_cacheYanteng Si2021-01-222-1/+2
| | | | | | | | | | This commit adds a prototype to fix error at W=1: arch/mips/mm/cache.c:129:6: error: no previous prototype for '__update_cache' [-Werror=missing-prototypes] Signed-off-by: Yanteng Si <siyanteng@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mm: abort uaccess retries upon fatal signalThomas Bogendoerfer2021-01-221-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | When there's a fatal signal pending, MIPS's do_page_fault() implementation returns. The intent is that we'll return to the faulting userspace instruction, delivering the signal on the way. However, if we take a fatal signal during fixing up a uaccess, this results in a return to the faulting kernel instruction, which will be instantly retried, resulting in the same fault being taken forever. As the task never reaches userspace, the signal is not delivered, and the task is left unkillable. While the task is stuck in this state, it can inhibit the forward progress of the system. To avoid this, we must ensure that when a fatal signal is pending, we apply any necessary fixup for a faulting kernel instruction. Thus we will return to an error path, and it is up to that code to make forward progress towards delivering the fatal signal. [ Description taken from commit 746a272e4414 ("ARM: 8692/1: mm: abort uaccess retries upon fatal signal") ] Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Mark Rutland <mark.rutland@arm.com>
* MIPS: IRQ: Add prototype for function init_IRQYanteng Si2021-01-191-0/+1
| | | | | | | | | | | This commit adds a prototype to fix error at W=1: arch/mips/kernel/irq.c:52:13: error: no previous prototype for 'init_IRQ' [-Werror=missing-prototypes] Signed-off-by: Yanteng Si <siyanteng@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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