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path: root/drivers/clk/socfpga
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-10-221-13/+0
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| * clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing2020-09-221-13/+0
* | clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clkDinh Nguyen2020-09-221-1/+1
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* clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen2020-06-191-1/+1
* clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen2020-06-191-1/+5
* clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen2020-05-264-0/+526
* clk: socfpga: add const to _ops data structuresDinh Nguyen2020-05-263-4/+4
* clk: socfpga: remove clk_ops enable/disable methodsDinh Nguyen2020-05-263-6/+0
* clk: socfpga: stratix10: use new parent data schemeDinh Nguyen2020-05-265-41/+146
* clk: socfpga: stratix10: simplify parameter passingDinh Nguyen2020-02-125-92/+57
* clk: stratix10: use do_div() for 64-bit calculationDinh Nguyen2020-02-121-1/+3
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-09-202-14/+17
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| * clk: socfpga: deindent code to proper indentationStephen Boyd2019-08-161-2/+2
| * clk: socfpga: Don't reference clk_init_data after registrationStephen Boyd2019-08-162-13/+16
* | clk: socfpga: stratix10: fix rate caclulationg for cnt_clksDinh Nguyen2019-08-141-1/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-1/+5
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| * clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen2019-06-251-2/+2
| * clk: socfpga: stratix10: add additional clocks needed for the NAND IPDinh Nguyen2019-06-251-1/+5
* | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2019-06-281-2/+2
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| * | clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen2019-06-251-2/+2
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* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner2019-06-051-10/+1
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-303-36/+3
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-303-33/+3
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13Thomas Gleixner2019-05-211-13/+1
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-153-0/+3
*---. Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', ...Stephen Boyd2019-03-083-9/+15
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| | | * clk: socfpga: Don't have get_parent for single parent opsStephen Boyd2019-01-241-9/+13
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| * / clk: socfpga: fix refcount leakYangtao Li2018-12-282-0/+2
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* | clk: socfpga: stratix10: fix naming convention for the fixed-clocksDinh Nguyen2019-01-151-10/+10
* | clk: socfpga: stratix10: fix rate calculation for pll clocksDinh Nguyen2019-01-111-1/+1
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* clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen2018-07-061-1/+1
* clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen2018-07-061-1/+6
* clk: socfpga: stratix10: suppress unbinding platform's clock driverDinh Nguyen2018-05-151-0/+1
* clk: socfpga: stratix10: use platform driver APIsDinh Nguyen2018-05-151-22/+17
* clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen2018-04-067-5/+853
* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
* clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen2017-06-192-1/+4
* clk: socfpga: allow for multiple parents on Arria10 periph clocksDinh Nguyen2016-02-222-9/+4
* clk: socfpga: fix __init annotationArnd Bergmann2016-02-081-1/+1
* clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen2015-08-242-4/+15
* clk: socfpga: switch to GENMASK()Andy Shevchenko2015-07-285-5/+4
* clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd2015-07-207-7/+6
* clk: socfpga: remove a stray tabDan Carpenter2015-06-091-1/+1
* clk: socfpga: make use of of_clk_parent_fill helper functionDinh Nguyen2015-06-052-11/+2
* clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen2015-05-216-1/+469
* clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen2015-05-212-5/+5
* clk: socfpga: Silence sparse warningStephen Boyd2015-05-141-1/+1
* clk: socfpga: Silence sparse warningStephen Boyd2015-05-141-1/+1
* Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-...Mike Turquette2014-05-123-4/+23
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| * clk: socfpga: add divider registers to the main pll outputsDinh Nguyen2014-05-123-4/+23
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 17:03:14 +0000