summaryrefslogtreecommitdiffstats
path: root/drivers/fpga/zynq-fpga.c
Commit message (Expand)AuthorAgeFilesLines
* fpga: mgr: Use standard dev_release for class driverRuss Weight2021-11-281-10/+6
* fpga: fix spelling mistakesTom Rix2021-07-211-3/+3
* fpga: zynq: Remove clk_get error message for probe deferShubhrajyoti Datta2020-03-301-1/+2
* fpga: Remove dev_err() usage after platform_get_irq()Stephen Boyd2019-10-041-3/+1
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285Thomas Gleixner2019-06-051-9/+1
* zynq-fpga: Only route PR via PCAP when requiredMike Looijmans2018-11-111-0/+4
* fpga: mgr: add devm_fpga_mgr_createAlan Tull2018-10-161-3/+2
* fpga: manager: change api, don't use drvdataAlan Tull2018-05-251-3/+11
* fpga: zynq: Add support for encrypted bitstreamsMoritz Fischer2017-03-171-3/+25
* fpga zynq: Use the scatterlist interfaceJason Gunthorpe2017-02-101-39/+135
* fpga zynq: Check the bitstream for validityJason Gunthorpe2017-02-101-0/+21
* fpga zynq: Check for errors after completing DMAJason Gunthorpe2017-02-101-22/+32
* fpga zynq: Fix incorrect ISR state on bootupJason Gunthorpe2016-11-291-7/+10
* fpga zynq: Remove priv->devJason Gunthorpe2016-11-291-11/+8
* fpga zynq: Add missing \n to messagesJason Gunthorpe2016-11-291-11/+11
* fpga-mgr: add fpga image information structAlan Tull2016-11-101-4/+6
* fpga: zynq-fpga: Fix issue with drvdata being overwritten.Moritz Fischer2015-10-231-3/+4
* fpga: zynq-fpga: Change fw format to handle bin instead of bit.Moritz Fischer2015-10-231-22/+2
* fpga: zynq-fpga: Fix unbalanced clock handlingMoritz Fischer2015-10-231-2/+2
* fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000Moritz Fischer2015-10-171-0/+533
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 16:30:52 +0000