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path: root/drivers/gpio/gpio-aspeed.c
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* gpio: fix aspeed_gpio unmask irqGovert Overgaauw2018-05-161-1/+1
| | | | | | | | | | | | | commit f241632fd087d3d9fbd5450f4d8c8604badd8348 upstream. The unmask function disables all interrupts in a bank when unmasking an interrupt. Only disable the given interrupt. Cc: stable@vger.kernel.org Signed-off-by: Govert Overgaauw <govert.overgaauw@prodrive-technologies.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* gpio: aspeed: remove redundant return value checkWei Yongjun2016-09-231-3/+0
| | | | | | | | | Remove unneeded error handling on the result of a call to platform_get_resource() when the value is passed to devm_ioremap_resource(). Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: aspeed: fix return value check in aspeed_gpio_probe()Wei Yongjun2016-09-151-2/+2
| | | | | | | | | | In case of error, the function devm_ioremap_resource() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: aspeed: add MODULE_LICENSE()Linus Walleij2016-09-131-0/+1
| | | | | | | | | | | | | The build complains about missing MODULE_LICENSE() in the Aspeed GPIO driver. The license is evident from the file header, put in "GPL". Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Alistair Popple <alistair@popple.id.au> Cc: Jeremy Kerr <jk@ozlabs.org> Cc: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* gpio: Add Aspeed driverJoel Stanley2016-09-071-0/+457
The Aspeed SoCs contain GPIOs banked by letter, where each bank contains 8 pins. The GPIO banks are then grouped in sets of four in the register layout. The implementation exposes multiple banks through the one driver and requests and releases pins via the pinctrl subsystem. The hardware supports generation of interrupts from all GPIO-capable pins. A number of hardware features are not yet supported: Configuration of interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance for output ports. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>