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* pinctrl: rockchip: fix mux route data for rk3568Jonas Karlman2023-01-171-10/+10
| | | | | | | | | | | | | | | | | | | IO mux selection is configured in PMU_GRF_SOC_CON4 and GRF_IOFUNC_SEL0-5 regs on RK3568. pwm0-2 is configured in PMU_GRF reg and the rest is configured in GRF_IOFUNC regs according to TRM [1]. Update mux route data to reflect this and use proper detection pin for UART1 IO mux M1. This fixes HDMITX IO mux M1 selection and makes it possible to enable HDMI CEC on my Radxa ROCK 3 Model A v1.31 board. [1] http://opensource.rock-chips.com/images/2/26/Rockchip_RK3568_TRM_Part1_V1.3-20220930P.PDF Fixes: c0dadc0e47a8 ("pinctrl: rockchip: add support for rk3568") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230110084636.1141740-1-jonas@kwiboo.se Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: rockchip: fix reading pull type on rk3568Jonas Karlman2023-01-161-1/+10
| | | | | | | | | | | | | | | | | When reading pinconf-pins from debugfs it fails to get the configured pull type on RK3568, "unsupported pinctrl type" error messages is also reported. Fix this by adding support for RK3568 in rockchip_get_pull, including a reverse of the pull-up value swap applied in rockchip_set_pull so that pull-up is correctly reported in pinconf-pins. Also update the workaround comment to reflect affected pins, GPIO0_D3-D6. Fixes: c0dadc0e47a8 ("pinctrl: rockchip: add support for rk3568") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20230110172955.1258840-1-jonas@kwiboo.se Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: nomadik: Add missing header(s)Andy Shevchenko2023-01-048-31/+54
| | | | | | | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Fixes: e5530adc17a7 ("pinctrl: Clean up headers") Cc: Randy Dunlap <rdunlap@infradead.org> Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221229100746.35047-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: sp7021: fix unused function warningArnd Bergmann2022-12-291-5/+2
| | | | | | | | | | | | | | | | sppctl_gpio_inv_get is only used from the debugfs code inside of an #ifdef, so we get a warning without that: drivers/pinctrl/sunplus/sppctl.c:393:12: error: 'sppctl_gpio_inv_get' defined but not used [-Werror=unused-function] 393 | static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset) | ^~~~~~~~~~~~~~~~~~~ Replace the #ifdef with an IS_ENABLED() check that avoids the warning. Fixes: aa74c44be19c ("pinctrl: Add driver for Sunplus SP7021") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20221215163822.542622-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v6.2-1' of ↵Linus Torvalds2022-12-1396-887/+3954
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The two large chunks is the header clean-up from Andy and the Qualcomm DT bindings clean-up from Krzysztof. Each which could give rise to conflicts, but I haven't seen any. The YAML conversions happening around the device tree is the biggest item in the series and is the result of Rob Herrings ambition to autovalidate these trees against strict schemas and it is paying off in lots of bugs found and ever prettier device trees. Sooner or later the transition will be complete, Krzysztof is fixing up all of the Qualcomm stuff, which is pretty voluminous. Core changes: - minor but nice and important documentation clean-ups New drivers: - subdriver for the Qualcomm SDM670 SoC - subdriver for the Intel Moorefield SoC - trivial support for the NXP Freescale i.MXRT1170 SoC Other changes and improvements - major clean-up of the Qualcomm pin control device tree bindings by Krzysztof - major header clean-up by Andy - some immutable irqchip clean-up for the Actions Semiconductor and Nuvoton drivers - GPIO helpers for The Cypress cy8c95x0 driver - bias handling in the Mediatek MT7986 driver - remove the unused pins-are-numbered concept that never flew" * tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits) pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions() dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered pinctrl: stm32: Remove check for pins-are-numbered pinctrl: mediatek: common: Remove check for pins-are-numbered pinctrl: qcom: remove duplicate included header files pinctrl: sunxi: d1: Add CAN bus pinmuxes pinctrl: loongson2: Fix some const correctness pinctrl: pinconf-generic: add missing of_node_put() pinctrl: intel: Enumerate PWM device when community has a capability pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() pwm: lpss: Allow other drivers to enable PWM LPSS pwm: lpss: Include headers we are the direct user of pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS pwm: Add a stub for devm_pwmchip_add() pinctrl: k210: call of_node_put() pinctrl: starfive: Use existing variable gpio dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching pinconf-generic: fix style issues in pin_config_param doc pinctrl: pinctrl-loongson2: fix Kconfig dependency ...
| * pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions()Gaosheng Cui2022-12-061-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The thunderbay_add_functions() will free memory of thunderbay_funcs when everything is ok, but thunderbay_funcs will not be freed when thunderbay_add_functions() fails, then there will be a memory leak, so we need to add kfree() when thunderbay_add_functions() fails to fix it. In addition, doing some cleaner works, moving kfree(funcs) from thunderbay_add_functions() to thunderbay_build_functions(). Fixes: 12422af8194d ("pinctrl: Add Intel Thunder Bay pinctrl driver") Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Reviewed-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20221129120126.1567338-1-cuigaosheng1@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: stm32: Remove check for pins-are-numberedBernhard Rosenkränzer2022-12-031-5/+0
| | | | | | | | | | | | | | | | | | | | | | Remove the check for the unnecessary pins-are-numbered DeviceTree property Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221129023401.278780-3-bero@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: mediatek: common: Remove check for pins-are-numberedBernhard Rosenkränzer2022-12-031-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the check for the unnecessary pins-are-numbered Devicetree property. Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20221129023401.278780-2-bero@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: remove duplicate included header filesye xingchen2022-11-283-3/+0
| | | | | | | | | | | | | | | | linux/seq_file.h is included more than once. Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202211221631577017318@zte.com.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'intel-pinctrl-v6.2-2' of ↵Linus Walleij2022-11-281-0/+29
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.2-2 * Enable PWM feature on Intel pin control IPs The following is an automated git shortlog grouped by driver: intel: - Enumerate PWM device when community has a capability pwm: - lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() - lpss: Allow other drivers to enable PWM LPSS - lpss: Include headers we are the direct user of - lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS - Add a stub for devm_pwmchip_add()
| | * pinctrl: intel: Enumerate PWM device when community has a capabilityAndy Shevchenko2022-11-221-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the Communities may have PWM capability. In such cases, enumerate the PWM device via respective driver. A user is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
| * | pinctrl: sunxi: d1: Add CAN bus pinmuxesFabien Poussin2022-11-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The D1 pin controller contains muxes for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the pin controller is the same across all SoC variants. Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221126191636.6673-1-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: loongson2: Fix some const correctnessLinus Walleij2022-11-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel robot using sparse is complaining like this: drivers/pinctrl/pinctrl-loongson2.c:212:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void *[noderef] __iomem reg @@ (...) I think the problem is simply that the register base is defined as void * __iomem instead of void __iomem * and this is because of the way const correctness works with pointer infix order. Fix it up. I think. Reported-by: kernel test robot <lkp@intel.com> Cc: zhanghongchen <zhanghongchen@loongson.cn> Cc: Yinbo Zhu <zhuyinbo@loongson.cn> Fixes: f73f88acbc18 ("pinctrl: pinctrl-loongson2: add pinctrl driver support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pinconf-generic: add missing of_node_put()ZhangPeng2022-11-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_node_put() needs to be called when jumping out of the loop, since for_each_available_child_of_node() will increase the refcount of node. Fixes: c7289500e29d ("pinctrl: pinconf-generic: scan also referenced phandle node") Signed-off-by: ZhangPeng <zhangpeng362@huawei.com> Link: https://lore.kernel.org/r/20221125070156.3535855-1-zhangpeng362@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: k210: call of_node_put()ZhangPeng2022-11-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since for_each_available_child_of_node() will increase the refcount of node, we need to call of_node_put() manually when breaking out of the iteration. Fixes: d4c34d09ab03 ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver") Signed-off-by: ZhangPeng <zhangpeng362@huawei.com> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Link: https://lore.kernel.org/r/20221122075853.2496680-1-zhangpeng362@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: starfive: Use existing variable gpioGeert Uytterhoeven2022-11-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the existing variable "gpio", instead of obtaining the hwirq number again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/3b6b8597792a393d0f21b8489dd933663dfd2b90.1669045778.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pinctrl-loongson2: fix Kconfig dependencyRen Zhijie2022-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_PINCTRL_LOONGSON2=y and CONFIG_OF is not set, gcc complained about undefined reference: drivers/pinctrl/pinctrl-loongson2.o: In function `pinconf_generic_dt_node_to_map_all': pinctrl-loongson2.c:(.text+0x1c4): undefined reference to `pinconf_generic_dt_node_to_map' To fix this error, add depends on OF to config PINCTRL_LOONGSON2. Fixes: f73f88acbc18 ("pinctrl: pinctrl-loongson2: add pinctrl driver support") Signed-off-by: Ren Zhijie <renzhijie2@huawei.com> Link: https://lore.kernel.org/r/20221121132608.230645-1-renzhijie2@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Merge tag 'renesas-pinctrl-for-v6.2-tag1' of ↵Linus Walleij2022-11-203-9/+7
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.2 - Use dynamic GPIO base on combined pincctrl/gpio controllers on SH/R-Mobile SoCs, - Miscellaneous improvements.
| | * | pinctrl: renesas: gpio: Use dynamic GPIO base if no function GPIOsGeert Uytterhoeven2022-11-171-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 502df79b860563d7 ("gpiolib: Warn on drivers still using static gpiobase allocation") in gpio/for-next, one or more warnings are printed during boot on systems where the pin controller also provides GPIO functionality: gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation. Fix this for ARM-based SH/R-Mobile SoCs by: 1. Taking into account a non-zero GPIO base in the various GPIO chip callbacks, 2. Switching to dynamic allocation of the GPIO base when support for legacy function GPIOs is not enabled. On SuperH SoCs using legacy function GPIOs, the GPIO bases of the GPIO controller and the GPIO function controller must not be changed, as all board files rely on the fixed GPIO_* and GPIO_FN_* definitions provided by the various <cpu/sh*.h> header files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/df2cf30ac4c3cbee726799f32b727c1ebe62819c.1668000684.git.geert+renesas@glider.be
| | * | pinctrl: renesas: rzg2l: remove unnecessary check from rzg2l_dt_node_to_map()Biju Das2022-11-151-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the unnecessary check from rzg2l_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221108191309.3908415-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | pinctrl: renesas: rzv2m: remove unnecessary check from rzv2m_dt_node_to_map()Biju Das2022-11-151-2/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the unnecessary check from rzv2m_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221108183223.3902097-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | Merge tag 'intel-pinctrl-v6.2-1' of ↵Linus Walleij2022-11-1811-82/+1004
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.2-1 * Add Intel Moorefield pin control driver * Deduplicate COMMUNITY() macro in the Intel pin control drivers * Switch Freescale GPIO driver to use fwnode instead of of_node * Miscellaneous clenups here and there The following is an automated git shortlog grouped by driver: alderlake: - Deduplicate COMMUNITY macro code cannonlake: - Deduplicate COMMUNITY macro code device property: - Introduce fwnode_device_is_compatible() helper icelake: - Deduplicate COMMUNITY macro code intel: - Add Intel Moorefield pin controller support - Use temporary variable for struct device - Use str_enable_disable() helper merrifield: - Use temporary variable for struct device qcom: - lpass-lpi: Add missed bitfield.h soc: - fsl: qe: Switch to use fwnode instead of of_node sunrisepoint: - Deduplicate COMMUNITY macro code tigerlake: - Deduplicate COMMUNITY macro code
| | * | pinctrl: intel: Add Intel Moorefield pin controller supportAndy Shevchenko2022-11-083-0/+928
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds pinctrl support for Intel Moorefield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver, which supports this pinctrl interface, will be submitted separately. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | pinctrl: merrifield: Use temporary variable for struct deviceAndy Shevchenko2022-11-031-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: intel: Use temporary variable for struct deviceAndy Shevchenko2022-11-031-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: qcom: lpass-lpi: Add missed bitfield.hAndy Shevchenko2022-11-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the cleanup change dropped the bitfield.h from the pinctrl-lpass-lpi.h, since it's not used there, but forgot to re-instantiate it in the C-file, where users are located. Fix this by adding missed bitfield.h to the C-file. Fixes: aa9430f8a6de ("pinctrl: qcom: Add missing header(s)") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | pinctrl: intel: Use str_enable_disable() helperAndy Shevchenko2022-10-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use str_enable_disable() helper instead of open coding the same. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
| | * | pinctrl: tigerlake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: sunrisepoint: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: icelake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: cannonlake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: alderlake: Deduplicate COMMUNITY macro codeAndy Shevchenko2022-10-261-24/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| * | | pinctrl: pinctrl-loongson2: add pinctrl driver supportzhanghongchen2022-11-173-0/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Loongson-2 SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing. There is currently no support for GPIO pin pull-up and pull-down. Signed-off-by: zhanghongchen <zhanghongchen@loongson.cn> Co-developed-by: Yinbo Zhu <zhuyinbo@loongson.cn> Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Link: https://lore.kernel.org/r/20221114024942.8111-1-zhuyinbo@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: Move for_each_maps() to namespace and hide iterator insideAndy Shevchenko2022-11-142-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First of all, while for_each_maps() is private to pin control subsystem it's still better to have it put into a namespace. Besides that, users are not relying on iterator variable, so hide it inside for-loop. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221111120048.42968-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: tegra: Separate Tegra194 instancesThierry Reding2022-11-143-148/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: freescale: Fix i.MXRT1050 pad namesJesse Taube2022-11-101-293/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pad names for the i.MXRT1050 were incorrect. Fix them. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Link: https://lore.kernel.org/r/20221107071511.2764628-7-Mr.Bossman075@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoCSam Shih2022-11-101-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") add SoC specify 'pull_type' attribute for bias configuration. This patch add pull_type attribute to pinctrl-mt7986.c, and make bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mediatek: extend pinctrl-moore to support new bias functionsSam Shih2022-11-101-7/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo and mtk_pinconf_bias_get_combo, and make the functions able to support almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. This patch enables pinctrl_moore to support these functions. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mediatek: fix the pinconf register offset of some pinsSam Shih2022-11-101-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the bias-pull-up, bias-pull-down and bias-disable register offset of mt7986 pin-42 to pin-49, in the original driver, the relative offset value was erroneously decremented by 1. Fixes: 360de6728064 ("pinctrl: mediatek: add support for MT7986 SoC") Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-5-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: nuvoton: wpcm450: Fix handling of inverted MFSEL bitsJonathan Neuschäfer2022-11-101-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0 selects the GPIO function and 1 selects the special function, in these two fields, 0 selects the special function and 1 selects the GPIO function. Adjust the code to handle this quirk. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-3-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: nuvoton: wpcm450: Refactor MFSEL setting codeJonathan Neuschäfer2022-11-101-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for the next patch, which makes the logic around setting/resetting bits in MFSEL a little more complicated, move that code to a new function Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-2-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: nuvoton: wpcm450: Convert irqchip to IRQCHIP_IMMUTABLEJonathan Neuschäfer2022-11-091-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6c846d026d490 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning for irqchips that are not marked with IRQCHIP_IMMUTABLE. Convert the pinctrl-wpcm450 driver to an immutable irqchip. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221031222833.201322-1-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: freescale: add pad wakeup configShenwei Wang2022-11-081-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add the logic to configure the pad wakeup function via the pin_config_set handler. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20221027130859.1444412-5-shenwei.wang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callbackBalsam CHIHI2022-11-071-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Use the mt8365_set_clr_mode() callback to fix the issue. Co-developed-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> Link: https://lore.kernel.org/r/20221021084708.1109986-3-bchihi@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken ↵Balsam CHIHI2022-11-072-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SET/CLR modes On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add mt8365_set_clr_mode() callback for such SoCs, so that instead of using the SET/CLR register, use the main R/W register to read/update/write the modes. Co-developed-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> Link: https://lore.kernel.org/r/20221021084708.1109986-2-bchihi@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | Merge tag 'intel-pinctrl-v6.1-2' of ↵Linus Walleij2022-10-2668-203/+392
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.1-2 * Add missing and remove unused headers in the pin control and GPIO drivers * Revise the pin control and GPIO headers
| | * | pinctrl: Clean up headersAndy Shevchenko2022-10-247-17/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a few things done: - include only the headers we are direct user of - when pointer is in use, provide a forward declaration - add missing headers - group generic headers and subsystem headers - sort each group alphabetically While at it, fix some awkward indentations. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| | * | pinctrl: intel: Add missing header(s)Andy Shevchenko2022-10-241-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: merrifield: Add missing header(s)Andy Shevchenko2022-10-241-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| | * | pinctrl: lynxpoint: Add missing header(s)Andy Shevchenko2022-10-241-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>