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path: root/drivers/spi/spi-dw.h
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* spi: dw: Add support for Intel Thunder Bay SPI controllerNandhini Srikandan2022-07-131-2/+1
* spi: dw: Add support for master mode selection for DWC SSI controllerNandhini Srikandan2022-07-131-7/+1
* spi: dw: Fix IP-core versions macroNandhini Srikandan2022-07-131-1/+1
* spi: dw: Define the capabilities in a continuous bit-flags setSerge Semin2021-11-161-1/+1
* spi: dw: Replace DWC_HSSI capability with IP-core version checkerSerge Semin2021-11-161-1/+0
* spi: dw: Introduce Synopsys IP-core versions interfaceSerge Semin2021-11-161-8/+28
* spi: dw: Convert to using the Bitfield access macrosSerge Semin2021-11-161-33/+31
* spi: dw: Put the driver entities naming in orderSerge Semin2021-11-161-72/+73
* spi: dw: Discard redundant DW SSI Frame Formats enumerationSerge Semin2021-11-161-9/+3
* spi: dw: Add support for 32-bits max xfer sizeDamien Le Moal2020-12-091-0/+5
* spi: dw: Introduce max mem-ops SPI bus frequency settingSerge Semin2020-10-081-0/+1
* spi: dw: Add memory operations supportSerge Semin2020-10-081-0/+13
* spi: dw: Add generic DW SSI status-check methodSerge Semin2020-10-081-0/+1
* spi: dw: Move num-of retries parameter to the header fileSerge Semin2020-10-081-0/+2
* spi: dw: De-assert chip-select on resetSerge Semin2020-10-081-3/+4
* spi: dw: Refactor data IO procedureSerge Semin2020-10-081-3/+2
* spi: dw: Add DW SPI controller config structureSerge Semin2020-10-081-0/+10
* spi: dw: Add DWC SSI capabilitySerge Semin2020-10-081-8/+1
* Merge series "spi: dw: Add full Baikal-T1 SPI Controllers support" from Serge...Mark Brown2020-09-291-23/+22
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| * spi: spi-dw: Remove extraneous lockingSerge Semin2020-09-291-1/+0
| * spi: dw: Add KeemBay Master capabilitySerge Semin2020-09-291-0/+8
| * spi: dw: Convert CS-override to DW SPI capabilitiesSerge Semin2020-09-291-1/+6
| * spi: dw: Discard DW SSI chip type storagesSerge Semin2020-09-291-1/+0
| * spi: dw: Use relaxed IO-methods to access FIFOsSerge Semin2020-09-291-14/+4
| * spi: dw: Clear IRQ status on DW SPI controller resetSerge Semin2020-09-291-3/+4
| * spi: dw: Discard IRQ threshold macroSerge Semin2020-09-291-3/+0
* | spi: dw-dma: Add one-by-one SG list entries transferSerge Semin2020-09-291-0/+1
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* spi: dw: Add support for RX sample delay registerLars Povlsen2020-09-081-0/+3
* spi: dw: Use regset32 DebugFS method to create regdump fileSerge Semin2020-05-291-0/+2
* spi: dw: Cleanup generic DW DMA code namingsSerge Semin2020-05-291-4/+4
* spi: dw: Move Non-DMA code to the DW PCIe-SPI driverSerge Semin2020-05-291-3/+11
* spi: dw: Use DMA max burst to set the request thresholdsSerge Semin2020-05-291-0/+2
* spi: dw: Locally wait for the DMA transfers completionSerge Semin2020-05-291-0/+2
* spi: dw: Discard dma_width member of the dw_spi structureSerge Semin2020-05-221-1/+0
* spi: dw: Discard unused void priv pointerSerge Semin2020-05-221-2/+0
* spi: dw: Discard static DW DMA slave structuresSerge Semin2020-05-221-2/+0
* spi: dw: Get rid of dma_inited flagAndy Shevchenko2020-05-071-1/+0
* spi: dw: Add Elkhart Lake PSE DMA supportJarkko Nikula2020-05-061-0/+1
* spi: dw: Propagate struct device pointer to ->dma_init() callbackAndy Shevchenko2020-05-061-1/+1
* spi: dw: Add 'mfld' suffix to Intel Medfield related routinesAndy Shevchenko2020-05-061-1/+2
* spi: dw: Downgrade interrupt.h to irqreturn.h where appropriateAndy Shevchenko2020-05-061-1/+1
* spi: dw: Move interrupt.h to spi-dw.h who is user of itAndy Shevchenko2020-05-061-0/+1
* spi: dw: Add support for DesignWare DWC_ssiWan Ahmad Zainie2020-05-051-0/+12
* spi: dw: Add update_cr0() callback to update CTRLR0Wan Ahmad Zainie2020-05-051-0/+5
* spi: dw: Fix typo in few registers nameWan Ahmad Zainie2020-05-051-4/+4
* spi: dw: remove unused dw_spi_chip handlingClement Leger2020-04-161-12/+0
* spi: spi-dw: Add lock protect dw_spi rx/tx to prevent concurrent callswuxu.wu2020-01-031-0/+1
* spi: dw: Drop GPIO headerLinus Walleij2019-10-301-1/+0
* dw: spi: add support for Amazon's Alpine spi controllerTalel Shenhar2018-10-111-0/+2
* spi: dw: export dw_spi_set_csAlexandre Belloni2018-07-301-0/+1
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