From e7cded27261297fb0d1fc53cad3c0e033d6a2c27 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 4 Jul 2017 14:37:03 +0200 Subject: phy: allwinner: phy-sun4i-usb: Add log when probing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When phy-sun4i-usb's probing fails, it does not print the reason in kernel log, forcing the developer to edit this driver to add info logs. This commit makes the kernel print the reason of phy-sun4i-usb's probing failure or a success message. Signed-off-by: Quentin Schulz Tested-by: Mylène Josserand Acked-by: Maxime Ripard Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/allwinner/phy-sun4i-usb.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index bbf06cfe5898..3bea17b9405a 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -653,19 +653,25 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det", GPIOD_IN); - if (IS_ERR(data->id_det_gpio)) + if (IS_ERR(data->id_det_gpio)) { + dev_err(dev, "Couldn't request ID GPIO\n"); return PTR_ERR(data->id_det_gpio); + } data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det", GPIOD_IN); - if (IS_ERR(data->vbus_det_gpio)) + if (IS_ERR(data->vbus_det_gpio)) { + dev_err(dev, "Couldn't request VBUS detect GPIO\n"); return PTR_ERR(data->vbus_det_gpio); + } if (of_find_property(np, "usb0_vbus_power-supply", NULL)) { data->vbus_power_supply = devm_power_supply_get_by_phandle(dev, "usb0_vbus_power-supply"); - if (IS_ERR(data->vbus_power_supply)) + if (IS_ERR(data->vbus_power_supply)) { + dev_err(dev, "Couldn't get the VBUS power supply\n"); return PTR_ERR(data->vbus_power_supply); + } if (!data->vbus_power_supply) return -EPROBE_DEFER; @@ -674,8 +680,10 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0); data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable); - if (IS_ERR(data->extcon)) + if (IS_ERR(data->extcon)) { + dev_err(dev, "Couldn't allocate our extcon device\n"); return PTR_ERR(data->extcon); + } ret = devm_extcon_dev_register(dev, data->extcon); if (ret) { @@ -690,8 +698,13 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) snprintf(name, sizeof(name), "usb%d_vbus", i); phy->vbus = devm_regulator_get_optional(dev, name); if (IS_ERR(phy->vbus)) { - if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) + if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) { + dev_err(dev, + "Couldn't get regulator %s... Deferring probe\n", + name); return -EPROBE_DEFER; + } + phy->vbus = NULL; } @@ -775,6 +788,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) return PTR_ERR(phy_provider); } + dev_dbg(dev, "successfully loaded\n"); + return 0; } -- cgit v1.2.3 From e88432e728ef3287b326031085893e5fc7878d2b Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Mon, 31 Jul 2017 12:04:11 +0530 Subject: dt-bindings: phy: qmp: Add output-clock-names The PHY outputs a clock that will act as the parent for the PHY's pipe clock. Add the name of this clock to the lane's DT node. Acked-by: Rob Herring Signed-off-by: Varadarajan Narayanan Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index e11c563a65ec..7dc6c635b71d 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -60,6 +60,8 @@ Required properties for child node: one for each entry in clock-names. - clock-names: Must contain following for pcie and usb qmp phys: "pipe" for pipe clock specific to each lane. + - clock-output-names: Name of the PHY clock that will be the parent for + the above pipe clock. - resets: a list of phandles and reset controller specifier pairs, one for each entry in reset-names. @@ -96,6 +98,7 @@ Example: clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; + clock-output-names = "pcie_0_pipe_clk_src"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "lane0"; }; -- cgit v1.2.3 From 2d66eab1837542bdb347f514df1cd05ec1fc2969 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Mon, 31 Jul 2017 12:04:12 +0530 Subject: dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074 IPQ8074 uses QMP PHY controller that provides support to PCIe and USB. Adding DT binding information for the same. Reviewed-by: Vivek Gautam Signed-off-by: Varadarajan Narayanan Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 7dc6c635b71d..b6a9f2b92bab 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. Required properties: - compatible: compatible list, contains: + "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. @@ -38,6 +39,8 @@ Required properties: "phy", "common", "cfg". For "qcom,msm8996-qmp-usb3-phy" must contain "phy", "common". + For "qcom,ipq8074-qmp-pcie-phy" must contain: + "phy", "common". - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. @@ -63,6 +66,11 @@ Required properties for child node: - clock-output-names: Name of the PHY clock that will be the parent for the above pipe clock. + For "qcom,ipq8074-qmp-pcie-phy": + - "pcie20_phy0_pipe_clk" Pipe Clock parent + (or) + "pcie20_phy1_pipe_clk" + - resets: a list of phandles and reset controller specifier pairs, one for each entry in reset-names. - reset-names: Must contain following for pcie qmp phys: -- cgit v1.2.3 From 2a9316b04605a0d47bafe50454d067a97b00dfef Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Mon, 31 Jul 2017 12:04:13 +0530 Subject: phy: qcom-qmp: Fix phy pipe clock name Presently, the phy pipe clock's name is assumed to be either usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the phy lane's number). However, this will not work if an SoC has more than one instance of the phy. Hence, instead of assuming the name of the clock, fetch it from the DT. Reviewed-by: Vivek Gautam Signed-off-by: Varadarajan Narayanan Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/qualcomm/phy-qcom-qmp.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 78ca62897784..3dd789198704 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -925,29 +925,28 @@ static int qcom_qmp_phy_clk_init(struct device *dev) * clk | +-------+ | +-----+ * +---------------+ */ -static int phy_pipe_clk_register(struct qcom_qmp *qmp, int id) +static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) { - char name[24]; struct clk_fixed_rate *fixed; struct clk_init_data init = { }; + int ret; - switch (qmp->cfg->type) { - case PHY_TYPE_USB3: - snprintf(name, sizeof(name), "usb3_phy_pipe_clk_src"); - break; - case PHY_TYPE_PCIE: - snprintf(name, sizeof(name), "pcie_%d_pipe_clk_src", id); - break; - default: + if ((qmp->cfg->type != PHY_TYPE_USB3) && + (qmp->cfg->type != PHY_TYPE_PCIE)) { /* not all phys register pipe clocks, so return success */ return 0; } + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(qmp->dev, "%s: No clock-output-names\n", np->name); + return ret; + } + fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); if (!fixed) return -ENOMEM; - init.name = name; init.ops = &clk_fixed_rate_ops; /* controllers using QMP phys use 125MHz pipe clock interface */ @@ -1122,7 +1121,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) * Register the pipe clock provided by phy. * See function description to see details of this pipe clock. */ - ret = phy_pipe_clk_register(qmp, id); + ret = phy_pipe_clk_register(qmp, child); if (ret) { dev_err(qmp->dev, "failed to register pipe clock source\n"); -- cgit v1.2.3 From eef243d04b2b69e032f145e1f165afb4160be3e5 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Mon, 31 Jul 2017 12:04:14 +0530 Subject: phy: qcom-qmp: Add support for IPQ8074 Add definitions required to enable QMP phy support for IPQ8074. Signed-off-by: smuthayy Signed-off-by: Varadarajan Narayanan Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/qualcomm/phy-qcom-qmp.c | 124 ++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 3dd789198704..0c6cb8819200 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -59,6 +59,7 @@ #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 +#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac #define QSERDES_COM_RESETSM_CNTRL 0x0b4 #define QSERDES_COM_RESTRIM_CTRL 0x0bc @@ -143,6 +144,11 @@ #define QPHY_LOCK_DETECT_CONFIG3 0x88 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 +#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 +#define QPHY_OSC_DTCT_ACTIONS 0x1AC +#define QPHY_RX_SIGDET_LVL 0x1D8 +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) @@ -382,6 +388,85 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), }; +static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), + QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), + QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), + QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), + QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), + QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), + QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), + QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), + QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), + QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), +}; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { /* phy-type - PCIE/UFS/USB */ @@ -580,6 +665,42 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .mask_pcs_ready = PHYSTATUS, }; +/* list of resets */ +static const char * const ipq8074_pciephy_reset_l[] = { + "phy", "common", +}; + +static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { + .type = PHY_TYPE_PCIE, + .nlanes = 1, + + .serdes_tbl = ipq8074_pcie_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), + .tx_tbl = ipq8074_pcie_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), + .rx_tbl = ipq8074_pcie_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), + .pcs_tbl = ipq8074_pcie_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), + .clk_list = NULL, + .num_clks = 0, + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = NULL, + .num_vregs = 0, + .regs = pciephy_regs_layout, + + .start_ctrl = SERDES_START | PCS_START, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .mask_pcs_ready = PHYSTATUS, + + .has_phy_com_ctrl = false, + .has_lane_rst = false, + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + static void qcom_qmp_phy_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], @@ -1048,6 +1169,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg, + }, { + .compatible = "qcom,ipq8074-qmp-pcie-phy", + .data = &ipq8074_pciephy_cfg, }, { }, }; -- cgit v1.2.3 From 8387c576b713bf677d59b7f16be64adb6b2de660 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Tue, 20 Jun 2017 11:27:18 +0530 Subject: phy: qcom-qmp: Fix failure path in phy_init functions Fixing the clk enable failure path in qcom_qmp_phy_init() and cleanup the reset control deassertion failure path in qcom_qmp_phy_com_init(). Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: Kishon Vijay Abraham I Signed-off-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/qualcomm/phy-qcom-qmp.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 0c6cb8819200..e17f0351ccc2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -775,8 +775,6 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp) if (ret) { dev_err(qmp->dev, "%s reset deassert failed\n", qmp->cfg->reset_list[i]); - while (--i >= 0) - reset_control_assert(qmp->resets[i]); goto err_rst; } } @@ -805,7 +803,7 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp) if (ret) { dev_err(qmp->dev, "phy common block init timed-out\n"); - goto err_com_init; + goto err_rst; } } @@ -813,11 +811,11 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp) return 0; -err_com_init: +err_rst: while (--i >= 0) reset_control_assert(qmp->resets[i]); -err_rst: mutex_unlock(&qmp->phy_mutex); + return ret; } @@ -870,14 +868,13 @@ static int qcom_qmp_phy_init(struct phy *phy) if (ret) { dev_err(qmp->dev, "failed to enable %s clk, err=%d\n", qmp->cfg->clk_list[i], ret); - while (--i >= 0) - clk_disable_unprepare(qmp->clks[i]); + goto err_clk; } } ret = qcom_qmp_phy_com_init(qmp); if (ret) - goto err_com_init; + goto err_clk; if (cfg->has_lane_rst) { ret = reset_control_deassert(qphy->lane_rst); @@ -925,7 +922,7 @@ err_pcs_ready: reset_control_assert(qphy->lane_rst); err_lane_rst: qcom_qmp_phy_com_exit(qmp); -err_com_init: +err_clk: while (--i >= 0) clk_disable_unprepare(qmp->clks[i]); -- cgit v1.2.3 From 325ce0fe58992b67edea103339e00b028e38e40e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 7 Aug 2017 12:11:02 +0300 Subject: phy: ti-pipe3: Use TRM recommended settings for SATA DPLL The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf Signed-off-by: Roger Quadros [nsekhar@ti.com: add exact TRM version to commit text] Signed-off-by: Sekhar Nori Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-ti-pipe3.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 9c84d32c6f60..0e564f32749f 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -118,12 +118,12 @@ static struct pipe3_dpll_map dpll_map_usb[] = { }; static struct pipe3_dpll_map dpll_map_sata[] = { - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ + {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */ + {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */ {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ + {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */ + {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */ + {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */ { }, /* Terminator */ }; -- cgit v1.2.3 From 44a6d6ce6436a2b827c93ac59a6187af0c381a48 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 3 Aug 2017 18:01:00 +0800 Subject: phy: phy-mt65xx-usb3: add PCIe PHY support This patch adds PCIe PHY setting part. Signed-off-by: Ryder Lee Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-mt65xx-usb3.c | 220 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 202 insertions(+), 18 deletions(-) diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c index 59b110f795c3..8ba69058491d 100644 --- a/drivers/phy/phy-mt65xx-usb3.c +++ b/drivers/phy/phy-mt65xx-usb3.c @@ -29,7 +29,7 @@ #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ /* u2 phy bank */ #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 -/* u3 phy banks */ +/* u3/pcie phy banks */ #define SSUSB_SIFSLV_V1_U3PHYD 0x000 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 @@ -99,6 +99,23 @@ #define P2C_RG_SESSEND BIT(4) #define P2C_RG_AVALID BIT(2) +#define U3P_U3_CHIP_GPIO_CTLD 0x0c +#define P3C_REG_IP_SW_RST BIT(31) +#define P3C_MCU_BUS_CK_GATE_EN BIT(30) +#define P3C_FORCE_IP_SW_RST BIT(29) + +#define U3P_U3_CHIP_GPIO_CTLE 0x10 +#define P3C_RG_SWRST_U3_PHYD BIT(25) +#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) + +#define U3P_U3_PHYA_REG0 0x000 +#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) +#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) + +#define U3P_U3_PHYA_REG1 0x004 +#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) +#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) + #define U3P_U3_PHYA_REG6 0x018 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) @@ -108,9 +125,40 @@ #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) #define U3P_U3_PHYA_DA_REG0 0x100 +#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) +#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) +#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) +#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) +#define U3P_U3_PHYA_DA_REG4 0x108 +#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) +#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) +#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) + +#define U3P_U3_PHYA_DA_REG5 0x10c +#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) +#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) +#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) +#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) + +#define U3P_U3_PHYA_DA_REG6 0x110 +#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG7 0x114 +#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG20 0x13c +#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) +#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG25 0x148 +#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) +#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) + #define U3P_U3_PHYD_LFPS1 0x00c #define P3D_RG_FWAKE_TH GENMASK(21, 16) #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) @@ -322,7 +370,7 @@ static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy, dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index); } -static void phy_instance_init(struct mt65xx_u3phy *u3phy, +static void u2_phy_instance_init(struct mt65xx_u3phy *u3phy, struct mt65xx_phy_instance *instance) { struct u2phy_banks *u2_banks = &instance->u2_banks; @@ -384,7 +432,7 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy, dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); } -static void phy_instance_power_on(struct mt65xx_u3phy *u3phy, +static void u2_phy_instance_power_on(struct mt65xx_u3phy *u3phy, struct mt65xx_phy_instance *instance) { struct u2phy_banks *u2_banks = &instance->u2_banks; @@ -420,7 +468,7 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy, dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); } -static void phy_instance_power_off(struct mt65xx_u3phy *u3phy, +static void u2_phy_instance_power_off(struct mt65xx_u3phy *u3phy, struct mt65xx_phy_instance *instance) { struct u2phy_banks *u2_banks = &instance->u2_banks; @@ -458,7 +506,7 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy, dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); } -static void phy_instance_exit(struct mt65xx_u3phy *u3phy, +static void u2_phy_instance_exit(struct mt65xx_u3phy *u3phy, struct mt65xx_phy_instance *instance) { struct u2phy_banks *u2_banks = &instance->u2_banks; @@ -477,21 +525,133 @@ static void phy_instance_exit(struct mt65xx_u3phy *u3phy, } } +static void pcie_phy_instance_init(struct mt65xx_u3phy *u3phy, + struct mt65xx_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + u32 tmp; + + if (u3phy->pdata->version != MT_PHY_V1) + return; + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); + tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); + tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); + + /* ref clk drive */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); + tmp &= ~P3A_RG_CLKDRV_AMP; + tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); + tmp &= ~P3A_RG_CLKDRV_OFF; + tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); + + /* SSC delta -5000ppm */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); + tmp &= ~P3A_RG_PLL_DELTA1_PE2H; + tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); + tmp &= ~P3A_RG_PLL_DELTA_PE2H; + tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); + + /* change pll BW 0.6M */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); + tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); + tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); + tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); + tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); + tmp &= ~P3A_RG_PLL_IR_PE2H; + tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); + tmp &= ~P3A_RG_PLL_BP_PE2H; + tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); + + /* Tx Detect Rx Timing: 10us -> 5us */ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); + tmp &= ~P3D_RG_RXDET_STB2_SET; + tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); + + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); + tmp &= ~P3D_RG_RXDET_STB2_SET_P3; + tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); + + /* wait for PCIe subsys register to active */ + usleep_range(2500, 3000); + dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index); +} + +static void pcie_phy_instance_power_on(struct mt65xx_u3phy *u3phy, + struct mt65xx_phy_instance *instance) +{ + struct u3phy_banks *bank = &instance->u3_banks; + u32 tmp; + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); + tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN | + P3C_REG_IP_SW_RST); + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); + tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); +} + +static void pcie_phy_instance_power_off(struct mt65xx_u3phy *u3phy, + struct mt65xx_phy_instance *instance) + +{ + struct u3phy_banks *bank = &instance->u3_banks; + u32 tmp; + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); + tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); + tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); +} + static void phy_v1_banks_init(struct mt65xx_u3phy *u3phy, struct mt65xx_phy_instance *instance) { struct u2phy_banks *u2_banks = &instance->u2_banks; struct u3phy_banks *u3_banks = &instance->u3_banks; - if (instance->type == PHY_TYPE_USB2) { + switch (instance->type) { + case PHY_TYPE_USB2: u2_banks->misc = NULL; u2_banks->fmreg = u3phy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; - } else if (instance->type == PHY_TYPE_USB3) { + break; + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: u3_banks->spllc = u3phy->sif_base + SSUSB_SIFSLV_V1_SPLLC; u3_banks->chip = NULL; u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; + break; + default: + dev_err(u3phy->dev, "incompatible PHY type\n"); + return; } } @@ -501,15 +661,22 @@ static void phy_v2_banks_init(struct mt65xx_u3phy *u3phy, struct u2phy_banks *u2_banks = &instance->u2_banks; struct u3phy_banks *u3_banks = &instance->u3_banks; - if (instance->type == PHY_TYPE_USB2) { + switch (instance->type) { + case PHY_TYPE_USB2: u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; - } else if (instance->type == PHY_TYPE_USB3) { + break; + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; + break; + default: + dev_err(u3phy->dev, "incompatible PHY type\n"); + return; } } @@ -531,10 +698,20 @@ static int mt65xx_phy_init(struct phy *phy) return ret; } - if (instance->type == PHY_TYPE_USB2) - phy_instance_init(u3phy, instance); - else + switch (instance->type) { + case PHY_TYPE_USB2: + u2_phy_instance_init(u3phy, instance); + break; + case PHY_TYPE_USB3: u3_phy_instance_init(u3phy, instance); + break; + case PHY_TYPE_PCIE: + pcie_phy_instance_init(u3phy, instance); + break; + default: + dev_err(u3phy->dev, "incompatible PHY type\n"); + return -EINVAL; + } return 0; } @@ -545,9 +722,12 @@ static int mt65xx_phy_power_on(struct phy *phy) struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); if (instance->type == PHY_TYPE_USB2) { - phy_instance_power_on(u3phy, instance); + u2_phy_instance_power_on(u3phy, instance); hs_slew_rate_calibrate(u3phy, instance); + } else if (instance->type == PHY_TYPE_PCIE) { + pcie_phy_instance_power_on(u3phy, instance); } + return 0; } @@ -557,7 +737,9 @@ static int mt65xx_phy_power_off(struct phy *phy) struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); if (instance->type == PHY_TYPE_USB2) - phy_instance_power_off(u3phy, instance); + u2_phy_instance_power_off(u3phy, instance); + else if (instance->type == PHY_TYPE_PCIE) + pcie_phy_instance_power_off(u3phy, instance); return 0; } @@ -568,7 +750,7 @@ static int mt65xx_phy_exit(struct phy *phy) struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); if (instance->type == PHY_TYPE_USB2) - phy_instance_exit(u3phy, instance); + u2_phy_instance_exit(u3phy, instance); clk_disable_unprepare(instance->ref_clk); clk_disable_unprepare(u3phy->u3phya_ref); @@ -601,7 +783,8 @@ static struct phy *mt65xx_phy_xlate(struct device *dev, instance->type = args->args[0]; if (!(instance->type == PHY_TYPE_USB2 || - instance->type == PHY_TYPE_USB3)) { + instance->type == PHY_TYPE_USB3 || + instance->type == PHY_TYPE_PCIE)) { dev_err(dev, "unsupported device type: %d\n", instance->type); return ERR_PTR(-EINVAL); } @@ -626,7 +809,7 @@ static const struct phy_ops mt65xx_u3phy_ops = { .owner = THIS_MODULE, }; -static const struct mt65xx_phy_pdata mt2701_pdata = { +static const struct mt65xx_phy_pdata tphy_v1_pdata = { .avoid_rx_sen_degradation = false, .version = MT_PHY_V1, }; @@ -642,9 +825,10 @@ static const struct mt65xx_phy_pdata mt8173_pdata = { }; static const struct of_device_id mt65xx_u3phy_id_table[] = { - { .compatible = "mediatek,mt2701-u3phy", .data = &mt2701_pdata }, + { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, { .compatible = "mediatek,mt2712-u3phy", .data = &mt2712_pdata }, { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, + { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, { }, }; MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table); -- cgit v1.2.3 From 4ab26cb66a8cb3c216b870a879a34c841f9c46ec Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 3 Aug 2017 18:01:01 +0800 Subject: phy: phy-mt65xx-usb3: add SATA PHY support This patch adds SATA setting part. Signed-off-by: Ryder Lee Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-mt65xx-usb3.c | 133 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 129 insertions(+), 4 deletions(-) diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c index 8ba69058491d..45291c12d069 100644 --- a/drivers/phy/phy-mt65xx-usb3.c +++ b/drivers/phy/phy-mt65xx-usb3.c @@ -29,7 +29,7 @@ #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ /* u2 phy bank */ #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 -/* u3/pcie phy banks */ +/* u3/pcie/sata phy banks */ #define SSUSB_SIFSLV_V1_U3PHYD 0x000 #define SSUSB_SIFSLV_V1_U3PHYA 0x200 @@ -199,6 +199,65 @@ #define U3P_SR_COEF_DIVISOR 1000 #define U3P_FM_DET_CYCLE_CNT 1024 +/* SATA register setting */ +#define PHYD_CTRL_SIGNAL_MODE4 0x1c +/* CDR Charge Pump P-path current adjustment */ +#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) +#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) +#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) +#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) + +#define PHYD_DESIGN_OPTION2 0x24 +/* Symbol lock count selection */ +#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) +#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) + +#define PHYD_DESIGN_OPTION9 0x40 +/* COMWAK GAP width window */ +#define RG_TG_MAX_MSK GENMASK(20, 16) +#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) +/* COMINIT GAP width window */ +#define RG_T2_MAX_MSK GENMASK(13, 8) +#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) +/* COMWAK GAP width window */ +#define RG_TG_MIN_MSK GENMASK(7, 5) +#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) +/* COMINIT GAP width window */ +#define RG_T2_MIN_MSK GENMASK(4, 0) +#define RG_T2_MIN_VAL(x) (0x1f & (x)) + +#define ANA_RG_CTRL_SIGNAL1 0x4c +/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ +#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) +#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) + +#define ANA_RG_CTRL_SIGNAL4 0x58 +#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) +#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) +/* Loop filter R1 resistance adjustment for Gen1 speed */ +#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) +#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) + +#define ANA_RG_CTRL_SIGNAL6 0x60 +/* I-path capacitance adjustment for Gen1 */ +#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) +#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) +#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) +#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) + +#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c +/* RX Gen1 LEQ tuning step */ +#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) +#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) + +#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 +#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) +#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) + +#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc +#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) +#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) + enum mt_phy_version { MT_PHY_V1 = 1, MT_PHY_V2, @@ -630,6 +689,64 @@ static void pcie_phy_instance_power_off(struct mt65xx_u3phy *u3phy, writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); } +static void sata_phy_instance_init(struct mt65xx_u3phy *u3phy, + struct mt65xx_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + void __iomem *phyd = u3_banks->phyd; + u32 tmp; + + /* charge current adjustment */ + tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); + tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); + tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); + writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); + + tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); + tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; + tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); + writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); + + tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); + tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; + tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); + writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); + + tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); + tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); + tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); + writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); + + tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); + tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); + tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); + writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); + + tmp = readl(phyd + PHYD_DESIGN_OPTION2); + tmp &= ~RG_LOCK_CNT_SEL_MSK; + tmp |= RG_LOCK_CNT_SEL_VAL(0x02); + writel(tmp, phyd + PHYD_DESIGN_OPTION2); + + tmp = readl(phyd + PHYD_DESIGN_OPTION9); + tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | + RG_T2_MAX_MSK | RG_TG_MAX_MSK); + tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | + RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e); + writel(tmp, phyd + PHYD_DESIGN_OPTION9); + + tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); + tmp &= ~RG_IDRV_0DB_GEN1_MSK; + tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); + writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); + + tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); + tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; + tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); + writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); + + dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index); +} + static void phy_v1_banks_init(struct mt65xx_u3phy *u3phy, struct mt65xx_phy_instance *instance) { @@ -649,6 +766,9 @@ static void phy_v1_banks_init(struct mt65xx_u3phy *u3phy, u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; break; + case PHY_TYPE_SATA: + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; + break; default: dev_err(u3phy->dev, "incompatible PHY type\n"); return; @@ -708,6 +828,9 @@ static int mt65xx_phy_init(struct phy *phy) case PHY_TYPE_PCIE: pcie_phy_instance_init(u3phy, instance); break; + case PHY_TYPE_SATA: + sata_phy_instance_init(u3phy, instance); + break; default: dev_err(u3phy->dev, "incompatible PHY type\n"); return -EINVAL; @@ -784,7 +907,8 @@ static struct phy *mt65xx_phy_xlate(struct device *dev, instance->type = args->args[0]; if (!(instance->type == PHY_TYPE_USB2 || instance->type == PHY_TYPE_USB3 || - instance->type == PHY_TYPE_PCIE)) { + instance->type == PHY_TYPE_PCIE || + instance->type == PHY_TYPE_SATA)) { dev_err(dev, "unsupported device type: %d\n", instance->type); return ERR_PTR(-EINVAL); } @@ -814,7 +938,7 @@ static const struct mt65xx_phy_pdata tphy_v1_pdata = { .version = MT_PHY_V1, }; -static const struct mt65xx_phy_pdata mt2712_pdata = { +static const struct mt65xx_phy_pdata tphy_v2_pdata = { .avoid_rx_sen_degradation = false, .version = MT_PHY_V2, }; @@ -826,9 +950,10 @@ static const struct mt65xx_phy_pdata mt8173_pdata = { static const struct of_device_id mt65xx_u3phy_id_table[] = { { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, - { .compatible = "mediatek,mt2712-u3phy", .data = &mt2712_pdata }, + { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, + { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, { }, }; MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table); -- cgit v1.2.3 From 7c6eac238622a4204717f100e2980b0e8d3d1fcd Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Thu, 3 Aug 2017 18:01:03 +0800 Subject: dt-bindings: phy-mt65xx-usb: supports PCIe, SATA and rename file add support for PCIe and SATA, also add some new compatibles. due to phy-mt65xx-usb.txt holds the bindings for all mediatek SoCs with T-PHY controller, change the name to phy-mtk-tphy.txt to reflect that. Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 137 -------------------- .../devicetree/bindings/phy/phy-mtk-tphy.txt | 144 +++++++++++++++++++++ 2 files changed, 144 insertions(+), 137 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt deleted file mode 100644 index 0acc5a99fb79..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt +++ /dev/null @@ -1,137 +0,0 @@ -mt65xx USB3.0 PHY binding --------------------------- - -This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC. - -Required properties (controller (parent) node): - - compatible : should be one of - "mediatek,mt2701-u3phy" - "mediatek,mt2712-u3phy" - "mediatek,mt8173-u3phy" - - clocks : (deprecated, use port's clocks instead) a list of phandle + - clock-specifier pairs, one for each entry in clock-names - - clock-names : (deprecated, use port's one instead) must contain - "u3phya_ref": for reference clock of usb3.0 analog phy. - -Required nodes : a sub-node is required for each port the controller - provides. Address range information including the usual - 'reg' property is used inside these nodes to describe - the controller's topology. - -Optional properties (controller (parent) node): - - reg : offset and length of register shared by multiple ports, - exclude port's private register. It is needed on mt2701 - and mt8173, but not on mt2712. - -Required properties (port (child) node): -- reg : address and length of the register set for the port. -- clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names -- clock-names : must contain - "ref": 48M reference clock for HighSpeed analog phy; and 26M - reference clock for SuperSpeed analog phy, sometimes is - 24M, 25M or 27M, depended on platform. -- #phy-cells : should be 1 (See second example) - cell after port phandle is phy type from: - - PHY_TYPE_USB2 - - PHY_TYPE_USB3 - -Example: - -u3phy: usb-phy@11290000 { - compatible = "mediatek,mt8173-u3phy"; - reg = <0 0x11290000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u2port0: usb-phy@11290800 { - reg = <0 0x11290800 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@11290900 { - reg = <0 0x11290800 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u2port1: usb-phy@11291000 { - reg = <0 0x11291000 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; -}; - -Specifying phy control of devices ---------------------------------- - -Device nodes should specify the configuration required in their "phys" -property, containing a phandle to the phy port node and a device type; -phy-names for each port are optional. - -Example: - -#include - -usb30: usb@11270000 { - ... - phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; - phy-names = "usb2-0", "usb3-0"; - ... -}; - - -Layout differences of banks between mt8173/mt2701 and mt2712 -------------------------------------------------------------- -mt8173 and mt2701: -port offset bank -shared 0x0000 SPLLC - 0x0100 FMREG -u2 port0 0x0800 U2PHY_COM -u3 port0 0x0900 U3PHYD - 0x0a00 U3PHYD_BANK2 - 0x0b00 U3PHYA - 0x0c00 U3PHYA_DA -u2 port1 0x1000 U2PHY_COM -u3 port1 0x1100 U3PHYD - 0x1200 U3PHYD_BANK2 - 0x1300 U3PHYA - 0x1400 U3PHYA_DA -u2 port2 0x1800 U2PHY_COM - ... - -mt2712: -port offset bank -u2 port0 0x0000 MISC - 0x0100 FMREG - 0x0300 U2PHY_COM -u3 port0 0x0700 SPLLC - 0x0800 CHIP - 0x0900 U3PHYD - 0x0a00 U3PHYD_BANK2 - 0x0b00 U3PHYA - 0x0c00 U3PHYA_DA -u2 port1 0x1000 MISC - 0x1100 FMREG - 0x1300 U2PHY_COM -u3 port1 0x1700 SPLLC - 0x1800 CHIP - 0x1900 U3PHYD - 0x1a00 U3PHYD_BANK2 - 0x1b00 U3PHYA - 0x1c00 U3PHYA_DA -u2 port2 0x2000 MISC - ... - - SPLLC shared by u3 ports and FMREG shared by u2 ports on -mt8173/mt2701 are put back into each port; a new bank MISC for -u2 ports and CHIP for u3 ports are added on mt2712. diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt new file mode 100644 index 000000000000..faf18084a33a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -0,0 +1,144 @@ +MediaTek T-PHY binding +-------------------------- + +T-phy controller supports physical layer functionality for a number of +controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. + +Required properties (controller (parent) node): + - compatible : should be one of + "mediatek,generic-tphy-v1" + "mediatek,generic-tphy-v2" + "mediatek,mt2701-u3phy" (deprecated) + "mediatek,mt2712-u3phy" (deprecated) + "mediatek,mt8173-u3phy"; + make use of "mediatek,generic-tphy-v1" on mt2701 instead and + "mediatek,generic-tphy-v2" on mt2712 instead. + - clocks : (deprecated, use port's clocks instead) a list of phandle + + clock-specifier pairs, one for each entry in clock-names + - clock-names : (deprecated, use port's one instead) must contain + "u3phya_ref": for reference clock of usb3.0 analog phy. + +Required nodes : a sub-node is required for each port the controller + provides. Address range information including the usual + 'reg' property is used inside these nodes to describe + the controller's topology. + +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. It is needed on mt2701 + and mt8173, but not on mt2712. + +Required properties (port (child) node): +- reg : address and length of the register set for the port. +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : must contain + "ref": 48M reference clock for HighSpeed analog phy; and 26M + reference clock for SuperSpeed analog phy, sometimes is + 24M, 25M or 27M, depended on platform. +- #phy-cells : should be 1 (See second example) + cell after port phandle is phy type from: + - PHY_TYPE_USB2 + - PHY_TYPE_USB3 + - PHY_TYPE_PCIE + - PHY_TYPE_SATA + +Example: + +u3phy: usb-phy@11290000 { + compatible = "mediatek,mt8173-u3phy"; + reg = <0 0x11290000 0 0x800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port0: usb-phy@11290800 { + reg = <0 0x11290800 0 0x100>; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11290900 { + reg = <0 0x11290800 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port1: usb-phy@11291000 { + reg = <0 0x11291000 0 0x100>; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; +}; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type; +phy-names for each port are optional. + +Example: + +#include + +usb30: usb@11270000 { + ... + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; + ... +}; + + +Layout differences of banks between mt8173/mt2701 and mt2712 +------------------------------------------------------------- +mt8173 and mt2701: +port offset bank +shared 0x0000 SPLLC + 0x0100 FMREG +u2 port0 0x0800 U2PHY_COM +u3 port0 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 U2PHY_COM +u3 port1 0x1100 U3PHYD + 0x1200 U3PHYD_BANK2 + 0x1300 U3PHYA + 0x1400 U3PHYA_DA +u2 port2 0x1800 U2PHY_COM + ... + +mt2712: +port offset bank +u2 port0 0x0000 MISC + 0x0100 FMREG + 0x0300 U2PHY_COM +u3 port0 0x0700 SPLLC + 0x0800 CHIP + 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 MISC + 0x1100 FMREG + 0x1300 U2PHY_COM +u3 port1 0x1700 SPLLC + 0x1800 CHIP + 0x1900 U3PHYD + 0x1a00 U3PHYD_BANK2 + 0x1b00 U3PHYA + 0x1c00 U3PHYA_DA +u2 port2 0x2000 MISC + ... + + SPLLC shared by u3 ports and FMREG shared by u2 ports on +mt8173/mt2701 are put back into each port; a new bank MISC for +u2 ports and CHIP for u3 ports are added on mt2712. -- cgit v1.2.3 From cd4ec4b03dc15b164390c9d3e02e64935c3dd369 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Thu, 3 Aug 2017 18:01:02 +0800 Subject: phy: phy-mt65xx-usb3: add mediatek directory and rename file The driver is actually for T-PHY which supports USB3.0, PCIe and SATA, and supports more SoCs now, but not just only for series of mt65xx SoCs, so the name of file, data struct, functions etc with 'mt65xx' may cause misunderstanding when new SoCs are supported. Here rename them to reflect the real functions and also enhance readability. And also update MAINTAINERS file to reflect the correct driver Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- MAINTAINERS | 2 +- drivers/phy/Kconfig | 9 +- drivers/phy/Makefile | 2 +- drivers/phy/mediatek/Kconfig | 14 + drivers/phy/mediatek/Makefile | 5 + drivers/phy/mediatek/phy-mtk-tphy.c | 1081 +++++++++++++++++++++++++++++++++++ drivers/phy/phy-mt65xx-usb3.c | 1081 ----------------------------------- 7 files changed, 1103 insertions(+), 1091 deletions(-) create mode 100644 drivers/phy/mediatek/Kconfig create mode 100644 drivers/phy/mediatek/Makefile create mode 100644 drivers/phy/mediatek/phy-mtk-tphy.c delete mode 100644 drivers/phy/phy-mt65xx-usb3.c diff --git a/MAINTAINERS b/MAINTAINERS index 205d3977ac46..428e5d0a3bca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1599,7 +1599,7 @@ M: Chunfeng Yun L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: drivers/phy/phy-mt65xx-usb3.c +F: drivers/phy/mediatek/phy-mtk-tphy.c ARM/MICREL KS8695 ARCHITECTURE M: Greg Ungerer diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c1807d4a0079..d16704e77e68 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -26,14 +26,6 @@ config PHY_LPC18XX_USB_OTG This driver is need for USB0 support on LPC18xx/43xx and takes care of enabling and clock setup. -config PHY_MT65XX_USB3 - tristate "Mediatek USB3.0 PHY Driver" - depends on ARCH_MEDIATEK && OF - select GENERIC_PHY - help - Say 'Y' here to add support for Mediatek USB3.0 PHY driver, - it supports multiple usb2.0 and usb3.0 ports. - config PHY_PISTACHIO_USB tristate "IMG Pistachio USB2.0 PHY driver" depends on MACH_PISTACHIO @@ -53,6 +45,7 @@ source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/marvell/Kconfig" +source "drivers/phy/mediatek/Kconfig" source "drivers/phy/motorola/Kconfig" source "drivers/phy/qualcomm/Kconfig" source "drivers/phy/renesas/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index f252201e0ec9..1c68189b2894 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -4,12 +4,12 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o -obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o obj-$(CONFIG_ARCH_SUNXI) += allwinner/ obj-$(CONFIG_ARCH_MESON) += amlogic/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_RENESAS) += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig new file mode 100644 index 000000000000..88ab4e25e34f --- /dev/null +++ b/drivers/phy/mediatek/Kconfig @@ -0,0 +1,14 @@ +# +# Phy drivers for Mediatek devices +# +config PHY_MTK_TPHY + tristate "MediaTek T-PHY Driver" + depends on ARCH_MEDIATEK && OF + select GENERIC_PHY + help + Say 'Y' here to add support for MediaTek T-PHY driver, + it supports multiple usb2.0, usb3.0 ports, PCIe and + SATA, and meanwhile supports two version T-PHY which have + different banks layout, the T-PHY with shared banks between + multi-ports is first version, otherwise is second veriosn, + so you can easily distinguish them by banks layout. diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile new file mode 100644 index 000000000000..763a92eefa00 --- /dev/null +++ b/drivers/phy/mediatek/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the phy drivers. +# + +obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c new file mode 100644 index 000000000000..e3baad78521f --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -0,0 +1,1081 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Chunfeng Yun + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* version V1 sub-banks offset base address */ +/* banks shared by multiple phys */ +#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ +#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ +/* u2 phy bank */ +#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 +/* u3/pcie/sata phy banks */ +#define SSUSB_SIFSLV_V1_U3PHYD 0x000 +#define SSUSB_SIFSLV_V1_U3PHYA 0x200 + +/* version V2 sub-banks offset base address */ +/* u2 phy banks */ +#define SSUSB_SIFSLV_V2_MISC 0x000 +#define SSUSB_SIFSLV_V2_U2FREQ 0x100 +#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 +/* u3/pcie/sata phy banks */ +#define SSUSB_SIFSLV_V2_SPLLC 0x000 +#define SSUSB_SIFSLV_V2_CHIP 0x100 +#define SSUSB_SIFSLV_V2_U3PHYD 0x200 +#define SSUSB_SIFSLV_V2_U3PHYA 0x400 + +#define U3P_USBPHYACR0 0x000 +#define PA0_RG_U2PLL_FORCE_ON BIT(15) +#define PA0_RG_USB20_INTR_EN BIT(5) + +#define U3P_USBPHYACR2 0x008 +#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) + +#define U3P_USBPHYACR5 0x014 +#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) +#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) +#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) +#define PA5_RG_U2_HS_100U_U3_EN BIT(11) + +#define U3P_USBPHYACR6 0x018 +#define PA6_RG_U2_BC11_SW_EN BIT(23) +#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) +#define PA6_RG_U2_SQTH GENMASK(3, 0) +#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) + +#define U3P_U2PHYACR4 0x020 +#define P2C_RG_USB20_GPIO_CTL BIT(9) +#define P2C_USB20_GPIO_MODE BIT(8) +#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) + +#define U3D_U2PHYDCR0 0x060 +#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) + +#define U3P_U2PHYDTM0 0x068 +#define P2C_FORCE_UART_EN BIT(26) +#define P2C_FORCE_DATAIN BIT(23) +#define P2C_FORCE_DM_PULLDOWN BIT(21) +#define P2C_FORCE_DP_PULLDOWN BIT(20) +#define P2C_FORCE_XCVRSEL BIT(19) +#define P2C_FORCE_SUSPENDM BIT(18) +#define P2C_FORCE_TERMSEL BIT(17) +#define P2C_RG_DATAIN GENMASK(13, 10) +#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) +#define P2C_RG_DMPULLDOWN BIT(7) +#define P2C_RG_DPPULLDOWN BIT(6) +#define P2C_RG_XCVRSEL GENMASK(5, 4) +#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) +#define P2C_RG_SUSPENDM BIT(3) +#define P2C_RG_TERMSEL BIT(2) +#define P2C_DTM0_PART_MASK \ + (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ + P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ + P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ + P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) + +#define U3P_U2PHYDTM1 0x06C +#define P2C_RG_UART_EN BIT(16) +#define P2C_RG_VBUSVALID BIT(5) +#define P2C_RG_SESSEND BIT(4) +#define P2C_RG_AVALID BIT(2) + +#define U3P_U3_CHIP_GPIO_CTLD 0x0c +#define P3C_REG_IP_SW_RST BIT(31) +#define P3C_MCU_BUS_CK_GATE_EN BIT(30) +#define P3C_FORCE_IP_SW_RST BIT(29) + +#define U3P_U3_CHIP_GPIO_CTLE 0x10 +#define P3C_RG_SWRST_U3_PHYD BIT(25) +#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) + +#define U3P_U3_PHYA_REG0 0x000 +#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) +#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) + +#define U3P_U3_PHYA_REG1 0x004 +#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) +#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) + +#define U3P_U3_PHYA_REG6 0x018 +#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) +#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) + +#define U3P_U3_PHYA_REG9 0x024 +#define P3A_RG_RX_DAC_MUX GENMASK(5, 1) +#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) + +#define U3P_U3_PHYA_DA_REG0 0x100 +#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) +#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) +#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) +#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) +#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) +#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) + +#define U3P_U3_PHYA_DA_REG4 0x108 +#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) +#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) +#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) + +#define U3P_U3_PHYA_DA_REG5 0x10c +#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) +#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) +#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) +#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) + +#define U3P_U3_PHYA_DA_REG6 0x110 +#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG7 0x114 +#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) +#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG20 0x13c +#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) +#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) + +#define U3P_U3_PHYA_DA_REG25 0x148 +#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) +#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) + +#define U3P_U3_PHYD_LFPS1 0x00c +#define P3D_RG_FWAKE_TH GENMASK(21, 16) +#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) + +#define U3P_U3_PHYD_CDR1 0x05c +#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) +#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) +#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) +#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) + +#define U3P_U3_PHYD_RXDET1 0x128 +#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) +#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) + +#define U3P_U3_PHYD_RXDET2 0x12c +#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) +#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) + +#define U3P_SPLLC_XTALCTL3 0x018 +#define XC3_RG_U3_XTAL_RX_PWD BIT(9) +#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) + +#define U3P_U2FREQ_FMCR0 0x00 +#define P2F_RG_MONCLK_SEL GENMASK(27, 26) +#define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) +#define P2F_RG_FREQDET_EN BIT(24) +#define P2F_RG_CYCLECNT GENMASK(23, 0) +#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) + +#define U3P_U2FREQ_VALUE 0x0c + +#define U3P_U2FREQ_FMMONR1 0x10 +#define P2F_USB_FM_VALID BIT(0) +#define P2F_RG_FRCK_EN BIT(8) + +#define U3P_REF_CLK 26 /* MHZ */ +#define U3P_SLEW_RATE_COEF 28 +#define U3P_SR_COEF_DIVISOR 1000 +#define U3P_FM_DET_CYCLE_CNT 1024 + +/* SATA register setting */ +#define PHYD_CTRL_SIGNAL_MODE4 0x1c +/* CDR Charge Pump P-path current adjustment */ +#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) +#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) +#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) +#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) + +#define PHYD_DESIGN_OPTION2 0x24 +/* Symbol lock count selection */ +#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) +#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) + +#define PHYD_DESIGN_OPTION9 0x40 +/* COMWAK GAP width window */ +#define RG_TG_MAX_MSK GENMASK(20, 16) +#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) +/* COMINIT GAP width window */ +#define RG_T2_MAX_MSK GENMASK(13, 8) +#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) +/* COMWAK GAP width window */ +#define RG_TG_MIN_MSK GENMASK(7, 5) +#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) +/* COMINIT GAP width window */ +#define RG_T2_MIN_MSK GENMASK(4, 0) +#define RG_T2_MIN_VAL(x) (0x1f & (x)) + +#define ANA_RG_CTRL_SIGNAL1 0x4c +/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ +#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) +#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) + +#define ANA_RG_CTRL_SIGNAL4 0x58 +#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) +#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) +/* Loop filter R1 resistance adjustment for Gen1 speed */ +#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) +#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) + +#define ANA_RG_CTRL_SIGNAL6 0x60 +/* I-path capacitance adjustment for Gen1 */ +#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) +#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) +#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) +#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) + +#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c +/* RX Gen1 LEQ tuning step */ +#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) +#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) + +#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 +#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) +#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) + +#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc +#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) +#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) + +enum mtk_phy_version { + MTK_PHY_V1 = 1, + MTK_PHY_V2, +}; + +struct mtk_phy_pdata { + /* avoid RX sensitivity level degradation only for mt8173 */ + bool avoid_rx_sen_degradation; + enum mtk_phy_version version; +}; + +struct u2phy_banks { + void __iomem *misc; + void __iomem *fmreg; + void __iomem *com; +}; + +struct u3phy_banks { + void __iomem *spllc; + void __iomem *chip; + void __iomem *phyd; /* include u3phyd_bank2 */ + void __iomem *phya; /* include u3phya_da */ +}; + +struct mtk_phy_instance { + struct phy *phy; + void __iomem *port_base; + union { + struct u2phy_banks u2_banks; + struct u3phy_banks u3_banks; + }; + struct clk *ref_clk; /* reference clock of anolog phy */ + u32 index; + u8 type; +}; + +struct mtk_tphy { + struct device *dev; + void __iomem *sif_base; /* only shared sif */ + /* deprecated, use @ref_clk instead in phy instance */ + struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ + const struct mtk_phy_pdata *pdata; + struct mtk_phy_instance **phys; + int nphys; +}; + +static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + void __iomem *fmreg = u2_banks->fmreg; + void __iomem *com = u2_banks->com; + int calibration_val; + int fm_out; + u32 tmp; + + /* enable USB ring oscillator */ + tmp = readl(com + U3P_USBPHYACR5); + tmp |= PA5_RG_U2_HSTX_SRCAL_EN; + writel(tmp, com + U3P_USBPHYACR5); + udelay(1); + + /*enable free run clock */ + tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); + tmp |= P2F_RG_FRCK_EN; + writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); + + /* set cycle count as 1024, and select u2 channel */ + tmp = readl(fmreg + U3P_U2FREQ_FMCR0); + tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); + tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); + if (tphy->pdata->version == MTK_PHY_V1) + tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); + + writel(tmp, fmreg + U3P_U2FREQ_FMCR0); + + /* enable frequency meter */ + tmp = readl(fmreg + U3P_U2FREQ_FMCR0); + tmp |= P2F_RG_FREQDET_EN; + writel(tmp, fmreg + U3P_U2FREQ_FMCR0); + + /* ignore return value */ + readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, + (tmp & P2F_USB_FM_VALID), 10, 200); + + fm_out = readl(fmreg + U3P_U2FREQ_VALUE); + + /* disable frequency meter */ + tmp = readl(fmreg + U3P_U2FREQ_FMCR0); + tmp &= ~P2F_RG_FREQDET_EN; + writel(tmp, fmreg + U3P_U2FREQ_FMCR0); + + /*disable free run clock */ + tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); + tmp &= ~P2F_RG_FRCK_EN; + writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); + + if (fm_out) { + /* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */ + tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF; + tmp /= fm_out; + calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); + } else { + /* if FM detection fail, set default value */ + calibration_val = 4; + } + dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n", + instance->index, fm_out, calibration_val); + + /* set HS slew rate */ + tmp = readl(com + U3P_USBPHYACR5); + tmp &= ~PA5_RG_U2_HSTX_SRCTRL; + tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); + writel(tmp, com + U3P_USBPHYACR5); + + /* disable USB ring oscillator */ + tmp = readl(com + U3P_USBPHYACR5); + tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; + writel(tmp, com + U3P_USBPHYACR5); +} + +static void u3_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + u32 tmp; + + /* gating PCIe Analog XTAL clock */ + tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); + tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; + writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); + + /* gating XSQ */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); + tmp &= ~P3A_RG_XTAL_EXT_EN_U3; + tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); + tmp &= ~P3A_RG_RX_DAC_MUX; + tmp |= P3A_RG_RX_DAC_MUX_VAL(4); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); + tmp &= ~P3A_RG_TX_EIDLE_CM; + tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); + + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); + tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); + tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); + + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); + tmp &= ~P3D_RG_FWAKE_TH; + tmp |= P3D_RG_FWAKE_TH_VAL(0x34); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); + + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); + tmp &= ~P3D_RG_RXDET_STB2_SET; + tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); + + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); + tmp &= ~P3D_RG_RXDET_STB2_SET_P3; + tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); +} + +static void u2_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + void __iomem *com = u2_banks->com; + u32 index = instance->index; + u32 tmp; + + /* switch to USB function. (system register, force ip into usb mode) */ + tmp = readl(com + U3P_U2PHYDTM0); + tmp &= ~P2C_FORCE_UART_EN; + tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); + writel(tmp, com + U3P_U2PHYDTM0); + + tmp = readl(com + U3P_U2PHYDTM1); + tmp &= ~P2C_RG_UART_EN; + writel(tmp, com + U3P_U2PHYDTM1); + + tmp = readl(com + U3P_USBPHYACR0); + tmp |= PA0_RG_USB20_INTR_EN; + writel(tmp, com + U3P_USBPHYACR0); + + /* disable switch 100uA current to SSUSB */ + tmp = readl(com + U3P_USBPHYACR5); + tmp &= ~PA5_RG_U2_HS_100U_U3_EN; + writel(tmp, com + U3P_USBPHYACR5); + + if (!index) { + tmp = readl(com + U3P_U2PHYACR4); + tmp &= ~P2C_U2_GPIO_CTR_MSK; + writel(tmp, com + U3P_U2PHYACR4); + } + + if (tphy->pdata->avoid_rx_sen_degradation) { + if (!index) { + tmp = readl(com + U3P_USBPHYACR2); + tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; + writel(tmp, com + U3P_USBPHYACR2); + + tmp = readl(com + U3D_U2PHYDCR0); + tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; + writel(tmp, com + U3D_U2PHYDCR0); + } else { + tmp = readl(com + U3D_U2PHYDCR0); + tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; + writel(tmp, com + U3D_U2PHYDCR0); + + tmp = readl(com + U3P_U2PHYDTM0); + tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; + writel(tmp, com + U3P_U2PHYDTM0); + } + } + + tmp = readl(com + U3P_USBPHYACR6); + tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ + tmp &= ~PA6_RG_U2_SQTH; + tmp |= PA6_RG_U2_SQTH_VAL(2); + writel(tmp, com + U3P_USBPHYACR6); + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); +} + +static void u2_phy_instance_power_on(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + void __iomem *com = u2_banks->com; + u32 index = instance->index; + u32 tmp; + + /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ + tmp = readl(com + U3P_U2PHYDTM0); + tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL); + tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK); + writel(tmp, com + U3P_U2PHYDTM0); + + /* OTG Enable */ + tmp = readl(com + U3P_USBPHYACR6); + tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; + writel(tmp, com + U3P_USBPHYACR6); + + tmp = readl(com + U3P_U2PHYDTM1); + tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; + tmp &= ~P2C_RG_SESSEND; + writel(tmp, com + U3P_U2PHYDTM1); + + if (tphy->pdata->avoid_rx_sen_degradation && index) { + tmp = readl(com + U3D_U2PHYDCR0); + tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; + writel(tmp, com + U3D_U2PHYDCR0); + + tmp = readl(com + U3P_U2PHYDTM0); + tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; + writel(tmp, com + U3P_U2PHYDTM0); + } + dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); +} + +static void u2_phy_instance_power_off(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + void __iomem *com = u2_banks->com; + u32 index = instance->index; + u32 tmp; + + tmp = readl(com + U3P_U2PHYDTM0); + tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); + tmp |= P2C_FORCE_SUSPENDM; + writel(tmp, com + U3P_U2PHYDTM0); + + /* OTG Disable */ + tmp = readl(com + U3P_USBPHYACR6); + tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; + writel(tmp, com + U3P_USBPHYACR6); + + /* let suspendm=0, set utmi into analog power down */ + tmp = readl(com + U3P_U2PHYDTM0); + tmp &= ~P2C_RG_SUSPENDM; + writel(tmp, com + U3P_U2PHYDTM0); + udelay(1); + + tmp = readl(com + U3P_U2PHYDTM1); + tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); + tmp |= P2C_RG_SESSEND; + writel(tmp, com + U3P_U2PHYDTM1); + + if (tphy->pdata->avoid_rx_sen_degradation && index) { + tmp = readl(com + U3D_U2PHYDCR0); + tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; + writel(tmp, com + U3D_U2PHYDCR0); + } + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); +} + +static void u2_phy_instance_exit(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + void __iomem *com = u2_banks->com; + u32 index = instance->index; + u32 tmp; + + if (tphy->pdata->avoid_rx_sen_degradation && index) { + tmp = readl(com + U3D_U2PHYDCR0); + tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; + writel(tmp, com + U3D_U2PHYDCR0); + + tmp = readl(com + U3P_U2PHYDTM0); + tmp &= ~P2C_FORCE_SUSPENDM; + writel(tmp, com + U3P_U2PHYDTM0); + } +} + +static void pcie_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + u32 tmp; + + if (tphy->pdata->version != MTK_PHY_V1) + return; + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); + tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); + tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); + + /* ref clk drive */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); + tmp &= ~P3A_RG_CLKDRV_AMP; + tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); + tmp &= ~P3A_RG_CLKDRV_OFF; + tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); + + /* SSC delta -5000ppm */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); + tmp &= ~P3A_RG_PLL_DELTA1_PE2H; + tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); + tmp &= ~P3A_RG_PLL_DELTA_PE2H; + tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); + + /* change pll BW 0.6M */ + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); + tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); + tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); + tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); + tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); + tmp &= ~P3A_RG_PLL_IR_PE2H; + tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); + + tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); + tmp &= ~P3A_RG_PLL_BP_PE2H; + tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); + writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); + + /* Tx Detect Rx Timing: 10us -> 5us */ + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); + tmp &= ~P3D_RG_RXDET_STB2_SET; + tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); + + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); + tmp &= ~P3D_RG_RXDET_STB2_SET_P3; + tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); + writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); + + /* wait for PCIe subsys register to active */ + usleep_range(2500, 3000); + dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); +} + +static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *bank = &instance->u3_banks; + u32 tmp; + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); + tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN | + P3C_REG_IP_SW_RST); + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); + tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); +} + +static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + +{ + struct u3phy_banks *bank = &instance->u3_banks; + u32 tmp; + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); + tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); + + tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); + tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; + writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); +} + +static void sata_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u3phy_banks *u3_banks = &instance->u3_banks; + void __iomem *phyd = u3_banks->phyd; + u32 tmp; + + /* charge current adjustment */ + tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); + tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); + tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); + writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); + + tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); + tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; + tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); + writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); + + tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); + tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; + tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); + writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); + + tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); + tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); + tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); + writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); + + tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); + tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); + tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); + writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); + + tmp = readl(phyd + PHYD_DESIGN_OPTION2); + tmp &= ~RG_LOCK_CNT_SEL_MSK; + tmp |= RG_LOCK_CNT_SEL_VAL(0x02); + writel(tmp, phyd + PHYD_DESIGN_OPTION2); + + tmp = readl(phyd + PHYD_DESIGN_OPTION9); + tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | + RG_T2_MAX_MSK | RG_TG_MAX_MSK); + tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | + RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e); + writel(tmp, phyd + PHYD_DESIGN_OPTION9); + + tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); + tmp &= ~RG_IDRV_0DB_GEN1_MSK; + tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); + writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); + + tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); + tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; + tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); + writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); + + dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); +} + +static void phy_v1_banks_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + struct u3phy_banks *u3_banks = &instance->u3_banks; + + switch (instance->type) { + case PHY_TYPE_USB2: + u2_banks->misc = NULL; + u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; + u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; + break; + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: + u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; + u3_banks->chip = NULL; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; + break; + case PHY_TYPE_SATA: + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; + break; + default: + dev_err(tphy->dev, "incompatible PHY type\n"); + return; + } +} + +static void phy_v2_banks_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + struct u3phy_banks *u3_banks = &instance->u3_banks; + + switch (instance->type) { + case PHY_TYPE_USB2: + u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; + u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; + u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; + break; + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; + break; + default: + dev_err(tphy->dev, "incompatible PHY type\n"); + return; + } +} + +static int mtk_phy_init(struct phy *phy) +{ + struct mtk_phy_instance *instance = phy_get_drvdata(phy); + struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); + int ret; + + ret = clk_prepare_enable(tphy->u3phya_ref); + if (ret) { + dev_err(tphy->dev, "failed to enable u3phya_ref\n"); + return ret; + } + + ret = clk_prepare_enable(instance->ref_clk); + if (ret) { + dev_err(tphy->dev, "failed to enable ref_clk\n"); + return ret; + } + + switch (instance->type) { + case PHY_TYPE_USB2: + u2_phy_instance_init(tphy, instance); + break; + case PHY_TYPE_USB3: + u3_phy_instance_init(tphy, instance); + break; + case PHY_TYPE_PCIE: + pcie_phy_instance_init(tphy, instance); + break; + case PHY_TYPE_SATA: + sata_phy_instance_init(tphy, instance); + break; + default: + dev_err(tphy->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + return 0; +} + +static int mtk_phy_power_on(struct phy *phy) +{ + struct mtk_phy_instance *instance = phy_get_drvdata(phy); + struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); + + if (instance->type == PHY_TYPE_USB2) { + u2_phy_instance_power_on(tphy, instance); + hs_slew_rate_calibrate(tphy, instance); + } else if (instance->type == PHY_TYPE_PCIE) { + pcie_phy_instance_power_on(tphy, instance); + } + + return 0; +} + +static int mtk_phy_power_off(struct phy *phy) +{ + struct mtk_phy_instance *instance = phy_get_drvdata(phy); + struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); + + if (instance->type == PHY_TYPE_USB2) + u2_phy_instance_power_off(tphy, instance); + else if (instance->type == PHY_TYPE_PCIE) + pcie_phy_instance_power_off(tphy, instance); + + return 0; +} + +static int mtk_phy_exit(struct phy *phy) +{ + struct mtk_phy_instance *instance = phy_get_drvdata(phy); + struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); + + if (instance->type == PHY_TYPE_USB2) + u2_phy_instance_exit(tphy, instance); + + clk_disable_unprepare(instance->ref_clk); + clk_disable_unprepare(tphy->u3phya_ref); + return 0; +} + +static struct phy *mtk_phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct mtk_tphy *tphy = dev_get_drvdata(dev); + struct mtk_phy_instance *instance = NULL; + struct device_node *phy_np = args->np; + int index; + + if (args->args_count != 1) { + dev_err(dev, "invalid number of cells in 'phy' property\n"); + return ERR_PTR(-EINVAL); + } + + for (index = 0; index < tphy->nphys; index++) + if (phy_np == tphy->phys[index]->phy->dev.of_node) { + instance = tphy->phys[index]; + break; + } + + if (!instance) { + dev_err(dev, "failed to find appropriate phy\n"); + return ERR_PTR(-EINVAL); + } + + instance->type = args->args[0]; + if (!(instance->type == PHY_TYPE_USB2 || + instance->type == PHY_TYPE_USB3 || + instance->type == PHY_TYPE_PCIE || + instance->type == PHY_TYPE_SATA)) { + dev_err(dev, "unsupported device type: %d\n", instance->type); + return ERR_PTR(-EINVAL); + } + + if (tphy->pdata->version == MTK_PHY_V1) { + phy_v1_banks_init(tphy, instance); + } else if (tphy->pdata->version == MTK_PHY_V2) { + phy_v2_banks_init(tphy, instance); + } else { + dev_err(dev, "phy version is not supported\n"); + return ERR_PTR(-EINVAL); + } + + return instance->phy; +} + +static const struct phy_ops mtk_tphy_ops = { + .init = mtk_phy_init, + .exit = mtk_phy_exit, + .power_on = mtk_phy_power_on, + .power_off = mtk_phy_power_off, + .owner = THIS_MODULE, +}; + +static const struct mtk_phy_pdata tphy_v1_pdata = { + .avoid_rx_sen_degradation = false, + .version = MTK_PHY_V1, +}; + +static const struct mtk_phy_pdata tphy_v2_pdata = { + .avoid_rx_sen_degradation = false, + .version = MTK_PHY_V2, +}; + +static const struct mtk_phy_pdata mt8173_pdata = { + .avoid_rx_sen_degradation = true, + .version = MTK_PHY_V1, +}; + +static const struct of_device_id mtk_tphy_id_table[] = { + { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, + { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, + { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, + { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, + { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, + { }, +}; +MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); + +static int mtk_tphy_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *child_np; + struct phy_provider *provider; + struct resource *sif_res; + struct mtk_tphy *tphy; + struct resource res; + int port, retval; + + match = of_match_node(mtk_tphy_id_table, pdev->dev.of_node); + if (!match) + return -EINVAL; + + tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); + if (!tphy) + return -ENOMEM; + + tphy->pdata = match->data; + tphy->nphys = of_get_child_count(np); + tphy->phys = devm_kcalloc(dev, tphy->nphys, + sizeof(*tphy->phys), GFP_KERNEL); + if (!tphy->phys) + return -ENOMEM; + + tphy->dev = dev; + platform_set_drvdata(pdev, tphy); + + if (tphy->pdata->version == MTK_PHY_V1) { + /* get banks shared by multiple phys */ + sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + tphy->sif_base = devm_ioremap_resource(dev, sif_res); + if (IS_ERR(tphy->sif_base)) { + dev_err(dev, "failed to remap sif regs\n"); + return PTR_ERR(tphy->sif_base); + } + } + + /* it's deprecated, make it optional for backward compatibility */ + tphy->u3phya_ref = devm_clk_get(dev, "u3phya_ref"); + if (IS_ERR(tphy->u3phya_ref)) { + if (PTR_ERR(tphy->u3phya_ref) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + tphy->u3phya_ref = NULL; + } + + port = 0; + for_each_child_of_node(np, child_np) { + struct mtk_phy_instance *instance; + struct phy *phy; + + instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); + if (!instance) { + retval = -ENOMEM; + goto put_child; + } + + tphy->phys[port] = instance; + + phy = devm_phy_create(dev, child_np, &mtk_tphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "failed to create phy\n"); + retval = PTR_ERR(phy); + goto put_child; + } + + retval = of_address_to_resource(child_np, 0, &res); + if (retval) { + dev_err(dev, "failed to get address resource(id-%d)\n", + port); + goto put_child; + } + + instance->port_base = devm_ioremap_resource(&phy->dev, &res); + if (IS_ERR(instance->port_base)) { + dev_err(dev, "failed to remap phy regs\n"); + retval = PTR_ERR(instance->port_base); + goto put_child; + } + + instance->phy = phy; + instance->index = port; + phy_set_drvdata(phy, instance); + port++; + + /* if deprecated clock is provided, ignore instance's one */ + if (tphy->u3phya_ref) + continue; + + instance->ref_clk = devm_clk_get(&phy->dev, "ref"); + if (IS_ERR(instance->ref_clk)) { + dev_err(dev, "failed to get ref_clk(id-%d)\n", port); + retval = PTR_ERR(instance->ref_clk); + goto put_child; + } + } + + provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); + + return PTR_ERR_OR_ZERO(provider); +put_child: + of_node_put(child_np); + return retval; +} + +static struct platform_driver mtk_tphy_driver = { + .probe = mtk_tphy_probe, + .driver = { + .name = "mtk-tphy", + .of_match_table = mtk_tphy_id_table, + }, +}; + +module_platform_driver(mtk_tphy_driver); + +MODULE_AUTHOR("Chunfeng Yun "); +MODULE_DESCRIPTION("MediaTek T-PHY driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c deleted file mode 100644 index 45291c12d069..000000000000 --- a/drivers/phy/phy-mt65xx-usb3.c +++ /dev/null @@ -1,1081 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Chunfeng Yun - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* version V1 sub-banks offset base address */ -/* banks shared by multiple phys */ -#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ -#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ -/* u2 phy bank */ -#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 -/* u3/pcie/sata phy banks */ -#define SSUSB_SIFSLV_V1_U3PHYD 0x000 -#define SSUSB_SIFSLV_V1_U3PHYA 0x200 - -/* version V2 sub-banks offset base address */ -/* u2 phy banks */ -#define SSUSB_SIFSLV_V2_MISC 0x000 -#define SSUSB_SIFSLV_V2_U2FREQ 0x100 -#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 -/* u3 phy banks */ -#define SSUSB_SIFSLV_V2_SPLLC 0x000 -#define SSUSB_SIFSLV_V2_CHIP 0x100 -#define SSUSB_SIFSLV_V2_U3PHYD 0x200 -#define SSUSB_SIFSLV_V2_U3PHYA 0x400 - -#define U3P_USBPHYACR0 0x000 -#define PA0_RG_U2PLL_FORCE_ON BIT(15) -#define PA0_RG_USB20_INTR_EN BIT(5) - -#define U3P_USBPHYACR2 0x008 -#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) - -#define U3P_USBPHYACR5 0x014 -#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) -#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) -#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) -#define PA5_RG_U2_HS_100U_U3_EN BIT(11) - -#define U3P_USBPHYACR6 0x018 -#define PA6_RG_U2_BC11_SW_EN BIT(23) -#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) -#define PA6_RG_U2_SQTH GENMASK(3, 0) -#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x)) - -#define U3P_U2PHYACR4 0x020 -#define P2C_RG_USB20_GPIO_CTL BIT(9) -#define P2C_USB20_GPIO_MODE BIT(8) -#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) - -#define U3D_U2PHYDCR0 0x060 -#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) - -#define U3P_U2PHYDTM0 0x068 -#define P2C_FORCE_UART_EN BIT(26) -#define P2C_FORCE_DATAIN BIT(23) -#define P2C_FORCE_DM_PULLDOWN BIT(21) -#define P2C_FORCE_DP_PULLDOWN BIT(20) -#define P2C_FORCE_XCVRSEL BIT(19) -#define P2C_FORCE_SUSPENDM BIT(18) -#define P2C_FORCE_TERMSEL BIT(17) -#define P2C_RG_DATAIN GENMASK(13, 10) -#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) -#define P2C_RG_DMPULLDOWN BIT(7) -#define P2C_RG_DPPULLDOWN BIT(6) -#define P2C_RG_XCVRSEL GENMASK(5, 4) -#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) -#define P2C_RG_SUSPENDM BIT(3) -#define P2C_RG_TERMSEL BIT(2) -#define P2C_DTM0_PART_MASK \ - (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ - P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ - P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ - P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) - -#define U3P_U2PHYDTM1 0x06C -#define P2C_RG_UART_EN BIT(16) -#define P2C_RG_VBUSVALID BIT(5) -#define P2C_RG_SESSEND BIT(4) -#define P2C_RG_AVALID BIT(2) - -#define U3P_U3_CHIP_GPIO_CTLD 0x0c -#define P3C_REG_IP_SW_RST BIT(31) -#define P3C_MCU_BUS_CK_GATE_EN BIT(30) -#define P3C_FORCE_IP_SW_RST BIT(29) - -#define U3P_U3_CHIP_GPIO_CTLE 0x10 -#define P3C_RG_SWRST_U3_PHYD BIT(25) -#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) - -#define U3P_U3_PHYA_REG0 0x000 -#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) -#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2) - -#define U3P_U3_PHYA_REG1 0x004 -#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) -#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29) - -#define U3P_U3_PHYA_REG6 0x018 -#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) -#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) - -#define U3P_U3_PHYA_REG9 0x024 -#define P3A_RG_RX_DAC_MUX GENMASK(5, 1) -#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) - -#define U3P_U3_PHYA_DA_REG0 0x100 -#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) -#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16) -#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) -#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12) -#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) -#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) - -#define U3P_U3_PHYA_DA_REG4 0x108 -#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) -#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) -#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6) - -#define U3P_U3_PHYA_DA_REG5 0x10c -#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) -#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28) -#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) -#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12) - -#define U3P_U3_PHYA_DA_REG6 0x110 -#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) -#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16) - -#define U3P_U3_PHYA_DA_REG7 0x114 -#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) -#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16) - -#define U3P_U3_PHYA_DA_REG20 0x13c -#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) -#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16) - -#define U3P_U3_PHYA_DA_REG25 0x148 -#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) -#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x)) - -#define U3P_U3_PHYD_LFPS1 0x00c -#define P3D_RG_FWAKE_TH GENMASK(21, 16) -#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16) - -#define U3P_U3_PHYD_CDR1 0x05c -#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) -#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) -#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) -#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) - -#define U3P_U3_PHYD_RXDET1 0x128 -#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) -#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9) - -#define U3P_U3_PHYD_RXDET2 0x12c -#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) -#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x)) - -#define U3P_SPLLC_XTALCTL3 0x018 -#define XC3_RG_U3_XTAL_RX_PWD BIT(9) -#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) - -#define U3P_U2FREQ_FMCR0 0x00 -#define P2F_RG_MONCLK_SEL GENMASK(27, 26) -#define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26) -#define P2F_RG_FREQDET_EN BIT(24) -#define P2F_RG_CYCLECNT GENMASK(23, 0) -#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x)) - -#define U3P_U2FREQ_VALUE 0x0c - -#define U3P_U2FREQ_FMMONR1 0x10 -#define P2F_USB_FM_VALID BIT(0) -#define P2F_RG_FRCK_EN BIT(8) - -#define U3P_REF_CLK 26 /* MHZ */ -#define U3P_SLEW_RATE_COEF 28 -#define U3P_SR_COEF_DIVISOR 1000 -#define U3P_FM_DET_CYCLE_CNT 1024 - -/* SATA register setting */ -#define PHYD_CTRL_SIGNAL_MODE4 0x1c -/* CDR Charge Pump P-path current adjustment */ -#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) -#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20) -#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) -#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8) - -#define PHYD_DESIGN_OPTION2 0x24 -/* Symbol lock count selection */ -#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) -#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4) - -#define PHYD_DESIGN_OPTION9 0x40 -/* COMWAK GAP width window */ -#define RG_TG_MAX_MSK GENMASK(20, 16) -#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16) -/* COMINIT GAP width window */ -#define RG_T2_MAX_MSK GENMASK(13, 8) -#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8) -/* COMWAK GAP width window */ -#define RG_TG_MIN_MSK GENMASK(7, 5) -#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5) -/* COMINIT GAP width window */ -#define RG_T2_MIN_MSK GENMASK(4, 0) -#define RG_T2_MIN_VAL(x) (0x1f & (x)) - -#define ANA_RG_CTRL_SIGNAL1 0x4c -/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ -#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) -#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8) - -#define ANA_RG_CTRL_SIGNAL4 0x58 -#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) -#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20) -/* Loop filter R1 resistance adjustment for Gen1 speed */ -#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) -#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8) - -#define ANA_RG_CTRL_SIGNAL6 0x60 -/* I-path capacitance adjustment for Gen1 */ -#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) -#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24) -#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) -#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x)) - -#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c -/* RX Gen1 LEQ tuning step */ -#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) -#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8) - -#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 -#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) -#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16) - -#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc -#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) -#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) - -enum mt_phy_version { - MT_PHY_V1 = 1, - MT_PHY_V2, -}; - -struct mt65xx_phy_pdata { - /* avoid RX sensitivity level degradation only for mt8173 */ - bool avoid_rx_sen_degradation; - enum mt_phy_version version; -}; - -struct u2phy_banks { - void __iomem *misc; - void __iomem *fmreg; - void __iomem *com; -}; - -struct u3phy_banks { - void __iomem *spllc; - void __iomem *chip; - void __iomem *phyd; /* include u3phyd_bank2 */ - void __iomem *phya; /* include u3phya_da */ -}; - -struct mt65xx_phy_instance { - struct phy *phy; - void __iomem *port_base; - union { - struct u2phy_banks u2_banks; - struct u3phy_banks u3_banks; - }; - struct clk *ref_clk; /* reference clock of anolog phy */ - u32 index; - u8 type; -}; - -struct mt65xx_u3phy { - struct device *dev; - void __iomem *sif_base; /* only shared sif */ - /* deprecated, use @ref_clk instead in phy instance */ - struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ - const struct mt65xx_phy_pdata *pdata; - struct mt65xx_phy_instance **phys; - int nphys; -}; - -static void hs_slew_rate_calibrate(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u2phy_banks *u2_banks = &instance->u2_banks; - void __iomem *fmreg = u2_banks->fmreg; - void __iomem *com = u2_banks->com; - int calibration_val; - int fm_out; - u32 tmp; - - /* enable USB ring oscillator */ - tmp = readl(com + U3P_USBPHYACR5); - tmp |= PA5_RG_U2_HSTX_SRCAL_EN; - writel(tmp, com + U3P_USBPHYACR5); - udelay(1); - - /*enable free run clock */ - tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); - tmp |= P2F_RG_FRCK_EN; - writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); - - /* set cycle count as 1024, and select u2 channel */ - tmp = readl(fmreg + U3P_U2FREQ_FMCR0); - tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); - tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT); - if (u3phy->pdata->version == MT_PHY_V1) - tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); - - writel(tmp, fmreg + U3P_U2FREQ_FMCR0); - - /* enable frequency meter */ - tmp = readl(fmreg + U3P_U2FREQ_FMCR0); - tmp |= P2F_RG_FREQDET_EN; - writel(tmp, fmreg + U3P_U2FREQ_FMCR0); - - /* ignore return value */ - readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, - (tmp & P2F_USB_FM_VALID), 10, 200); - - fm_out = readl(fmreg + U3P_U2FREQ_VALUE); - - /* disable frequency meter */ - tmp = readl(fmreg + U3P_U2FREQ_FMCR0); - tmp &= ~P2F_RG_FREQDET_EN; - writel(tmp, fmreg + U3P_U2FREQ_FMCR0); - - /*disable free run clock */ - tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); - tmp &= ~P2F_RG_FRCK_EN; - writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); - - if (fm_out) { - /* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */ - tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF; - tmp /= fm_out; - calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); - } else { - /* if FM detection fail, set default value */ - calibration_val = 4; - } - dev_dbg(u3phy->dev, "phy:%d, fm_out:%d, calib:%d\n", - instance->index, fm_out, calibration_val); - - /* set HS slew rate */ - tmp = readl(com + U3P_USBPHYACR5); - tmp &= ~PA5_RG_U2_HSTX_SRCTRL; - tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val); - writel(tmp, com + U3P_USBPHYACR5); - - /* disable USB ring oscillator */ - tmp = readl(com + U3P_USBPHYACR5); - tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN; - writel(tmp, com + U3P_USBPHYACR5); -} - -static void u3_phy_instance_init(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u3phy_banks *u3_banks = &instance->u3_banks; - u32 tmp; - - /* gating PCIe Analog XTAL clock */ - tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); - tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD; - writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); - - /* gating XSQ */ - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); - tmp &= ~P3A_RG_XTAL_EXT_EN_U3; - tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); - tmp &= ~P3A_RG_RX_DAC_MUX; - tmp |= P3A_RG_RX_DAC_MUX_VAL(4); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); - tmp &= ~P3A_RG_TX_EIDLE_CM; - tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); - - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); - tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1); - tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3); - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); - - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); - tmp &= ~P3D_RG_FWAKE_TH; - tmp |= P3D_RG_FWAKE_TH_VAL(0x34); - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); - - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); - tmp &= ~P3D_RG_RXDET_STB2_SET; - tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); - - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); - tmp &= ~P3D_RG_RXDET_STB2_SET_P3; - tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); - - dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index); -} - -static void u2_phy_instance_init(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u2phy_banks *u2_banks = &instance->u2_banks; - void __iomem *com = u2_banks->com; - u32 index = instance->index; - u32 tmp; - - /* switch to USB function. (system register, force ip into usb mode) */ - tmp = readl(com + U3P_U2PHYDTM0); - tmp &= ~P2C_FORCE_UART_EN; - tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); - writel(tmp, com + U3P_U2PHYDTM0); - - tmp = readl(com + U3P_U2PHYDTM1); - tmp &= ~P2C_RG_UART_EN; - writel(tmp, com + U3P_U2PHYDTM1); - - tmp = readl(com + U3P_USBPHYACR0); - tmp |= PA0_RG_USB20_INTR_EN; - writel(tmp, com + U3P_USBPHYACR0); - - /* disable switch 100uA current to SSUSB */ - tmp = readl(com + U3P_USBPHYACR5); - tmp &= ~PA5_RG_U2_HS_100U_U3_EN; - writel(tmp, com + U3P_USBPHYACR5); - - if (!index) { - tmp = readl(com + U3P_U2PHYACR4); - tmp &= ~P2C_U2_GPIO_CTR_MSK; - writel(tmp, com + U3P_U2PHYACR4); - } - - if (u3phy->pdata->avoid_rx_sen_degradation) { - if (!index) { - tmp = readl(com + U3P_USBPHYACR2); - tmp |= PA2_RG_SIF_U2PLL_FORCE_EN; - writel(tmp, com + U3P_USBPHYACR2); - - tmp = readl(com + U3D_U2PHYDCR0); - tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; - writel(tmp, com + U3D_U2PHYDCR0); - } else { - tmp = readl(com + U3D_U2PHYDCR0); - tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; - writel(tmp, com + U3D_U2PHYDCR0); - - tmp = readl(com + U3P_U2PHYDTM0); - tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; - writel(tmp, com + U3P_U2PHYDTM0); - } - } - - tmp = readl(com + U3P_USBPHYACR6); - tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */ - tmp &= ~PA6_RG_U2_SQTH; - tmp |= PA6_RG_U2_SQTH_VAL(2); - writel(tmp, com + U3P_USBPHYACR6); - - dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); -} - -static void u2_phy_instance_power_on(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u2phy_banks *u2_banks = &instance->u2_banks; - void __iomem *com = u2_banks->com; - u32 index = instance->index; - u32 tmp; - - /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ - tmp = readl(com + U3P_U2PHYDTM0); - tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL); - tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK); - writel(tmp, com + U3P_U2PHYDTM0); - - /* OTG Enable */ - tmp = readl(com + U3P_USBPHYACR6); - tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; - writel(tmp, com + U3P_USBPHYACR6); - - tmp = readl(com + U3P_U2PHYDTM1); - tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; - tmp &= ~P2C_RG_SESSEND; - writel(tmp, com + U3P_U2PHYDTM1); - - if (u3phy->pdata->avoid_rx_sen_degradation && index) { - tmp = readl(com + U3D_U2PHYDCR0); - tmp |= P2C_RG_SIF_U2PLL_FORCE_ON; - writel(tmp, com + U3D_U2PHYDCR0); - - tmp = readl(com + U3P_U2PHYDTM0); - tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM; - writel(tmp, com + U3P_U2PHYDTM0); - } - dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); -} - -static void u2_phy_instance_power_off(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u2phy_banks *u2_banks = &instance->u2_banks; - void __iomem *com = u2_banks->com; - u32 index = instance->index; - u32 tmp; - - tmp = readl(com + U3P_U2PHYDTM0); - tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); - tmp |= P2C_FORCE_SUSPENDM; - writel(tmp, com + U3P_U2PHYDTM0); - - /* OTG Disable */ - tmp = readl(com + U3P_USBPHYACR6); - tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; - writel(tmp, com + U3P_USBPHYACR6); - - /* let suspendm=0, set utmi into analog power down */ - tmp = readl(com + U3P_U2PHYDTM0); - tmp &= ~P2C_RG_SUSPENDM; - writel(tmp, com + U3P_U2PHYDTM0); - udelay(1); - - tmp = readl(com + U3P_U2PHYDTM1); - tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); - tmp |= P2C_RG_SESSEND; - writel(tmp, com + U3P_U2PHYDTM1); - - if (u3phy->pdata->avoid_rx_sen_degradation && index) { - tmp = readl(com + U3D_U2PHYDCR0); - tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; - writel(tmp, com + U3D_U2PHYDCR0); - } - - dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); -} - -static void u2_phy_instance_exit(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u2phy_banks *u2_banks = &instance->u2_banks; - void __iomem *com = u2_banks->com; - u32 index = instance->index; - u32 tmp; - - if (u3phy->pdata->avoid_rx_sen_degradation && index) { - tmp = readl(com + U3D_U2PHYDCR0); - tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; - writel(tmp, com + U3D_U2PHYDCR0); - - tmp = readl(com + U3P_U2PHYDTM0); - tmp &= ~P2C_FORCE_SUSPENDM; - writel(tmp, com + U3P_U2PHYDTM0); - } -} - -static void pcie_phy_instance_init(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u3phy_banks *u3_banks = &instance->u3_banks; - u32 tmp; - - if (u3phy->pdata->version != MT_PHY_V1) - return; - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); - tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); - tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); - - /* ref clk drive */ - tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); - tmp &= ~P3A_RG_CLKDRV_AMP; - tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); - tmp &= ~P3A_RG_CLKDRV_OFF; - tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); - - /* SSC delta -5000ppm */ - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); - tmp &= ~P3A_RG_PLL_DELTA1_PE2H; - tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); - tmp &= ~P3A_RG_PLL_DELTA_PE2H; - tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); - - /* change pll BW 0.6M */ - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); - tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H); - tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); - tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H); - tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); - tmp &= ~P3A_RG_PLL_IR_PE2H; - tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); - - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); - tmp &= ~P3A_RG_PLL_BP_PE2H; - tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa); - writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); - - /* Tx Detect Rx Timing: 10us -> 5us */ - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); - tmp &= ~P3D_RG_RXDET_STB2_SET; - tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10); - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); - - tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); - tmp &= ~P3D_RG_RXDET_STB2_SET_P3; - tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10); - writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); - - /* wait for PCIe subsys register to active */ - usleep_range(2500, 3000); - dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index); -} - -static void pcie_phy_instance_power_on(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u3phy_banks *bank = &instance->u3_banks; - u32 tmp; - - tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); - tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN | - P3C_REG_IP_SW_RST); - writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); - - tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); - tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); - writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); -} - -static void pcie_phy_instance_power_off(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) - -{ - struct u3phy_banks *bank = &instance->u3_banks; - u32 tmp; - - tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); - tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST; - writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); - - tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); - tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD; - writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); -} - -static void sata_phy_instance_init(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u3phy_banks *u3_banks = &instance->u3_banks; - void __iomem *phyd = u3_banks->phyd; - u32 tmp; - - /* charge current adjustment */ - tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6); - tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK); - tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a); - writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6); - - tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4); - tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK; - tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18); - writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4); - - tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5); - tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK; - tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06); - writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5); - - tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4); - tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK); - tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07); - writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4); - - tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4); - tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK); - tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02); - writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4); - - tmp = readl(phyd + PHYD_DESIGN_OPTION2); - tmp &= ~RG_LOCK_CNT_SEL_MSK; - tmp |= RG_LOCK_CNT_SEL_VAL(0x02); - writel(tmp, phyd + PHYD_DESIGN_OPTION2); - - tmp = readl(phyd + PHYD_DESIGN_OPTION9); - tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK | - RG_T2_MAX_MSK | RG_TG_MAX_MSK); - tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) | - RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e); - writel(tmp, phyd + PHYD_DESIGN_OPTION9); - - tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1); - tmp &= ~RG_IDRV_0DB_GEN1_MSK; - tmp |= RG_IDRV_0DB_GEN1_VAL(0x20); - writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1); - - tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1); - tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK; - tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03); - writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1); - - dev_dbg(u3phy->dev, "%s(%d)\n", __func__, instance->index); -} - -static void phy_v1_banks_init(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u2phy_banks *u2_banks = &instance->u2_banks; - struct u3phy_banks *u3_banks = &instance->u3_banks; - - switch (instance->type) { - case PHY_TYPE_USB2: - u2_banks->misc = NULL; - u2_banks->fmreg = u3phy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; - u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; - break; - case PHY_TYPE_USB3: - case PHY_TYPE_PCIE: - u3_banks->spllc = u3phy->sif_base + SSUSB_SIFSLV_V1_SPLLC; - u3_banks->chip = NULL; - u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; - u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; - break; - case PHY_TYPE_SATA: - u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; - break; - default: - dev_err(u3phy->dev, "incompatible PHY type\n"); - return; - } -} - -static void phy_v2_banks_init(struct mt65xx_u3phy *u3phy, - struct mt65xx_phy_instance *instance) -{ - struct u2phy_banks *u2_banks = &instance->u2_banks; - struct u3phy_banks *u3_banks = &instance->u3_banks; - - switch (instance->type) { - case PHY_TYPE_USB2: - u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; - u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; - u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; - break; - case PHY_TYPE_USB3: - case PHY_TYPE_PCIE: - u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; - u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; - u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; - u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; - break; - default: - dev_err(u3phy->dev, "incompatible PHY type\n"); - return; - } -} - -static int mt65xx_phy_init(struct phy *phy) -{ - struct mt65xx_phy_instance *instance = phy_get_drvdata(phy); - struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); - int ret; - - ret = clk_prepare_enable(u3phy->u3phya_ref); - if (ret) { - dev_err(u3phy->dev, "failed to enable u3phya_ref\n"); - return ret; - } - - ret = clk_prepare_enable(instance->ref_clk); - if (ret) { - dev_err(u3phy->dev, "failed to enable ref_clk\n"); - return ret; - } - - switch (instance->type) { - case PHY_TYPE_USB2: - u2_phy_instance_init(u3phy, instance); - break; - case PHY_TYPE_USB3: - u3_phy_instance_init(u3phy, instance); - break; - case PHY_TYPE_PCIE: - pcie_phy_instance_init(u3phy, instance); - break; - case PHY_TYPE_SATA: - sata_phy_instance_init(u3phy, instance); - break; - default: - dev_err(u3phy->dev, "incompatible PHY type\n"); - return -EINVAL; - } - - return 0; -} - -static int mt65xx_phy_power_on(struct phy *phy) -{ - struct mt65xx_phy_instance *instance = phy_get_drvdata(phy); - struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); - - if (instance->type == PHY_TYPE_USB2) { - u2_phy_instance_power_on(u3phy, instance); - hs_slew_rate_calibrate(u3phy, instance); - } else if (instance->type == PHY_TYPE_PCIE) { - pcie_phy_instance_power_on(u3phy, instance); - } - - return 0; -} - -static int mt65xx_phy_power_off(struct phy *phy) -{ - struct mt65xx_phy_instance *instance = phy_get_drvdata(phy); - struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); - - if (instance->type == PHY_TYPE_USB2) - u2_phy_instance_power_off(u3phy, instance); - else if (instance->type == PHY_TYPE_PCIE) - pcie_phy_instance_power_off(u3phy, instance); - - return 0; -} - -static int mt65xx_phy_exit(struct phy *phy) -{ - struct mt65xx_phy_instance *instance = phy_get_drvdata(phy); - struct mt65xx_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); - - if (instance->type == PHY_TYPE_USB2) - u2_phy_instance_exit(u3phy, instance); - - clk_disable_unprepare(instance->ref_clk); - clk_disable_unprepare(u3phy->u3phya_ref); - return 0; -} - -static struct phy *mt65xx_phy_xlate(struct device *dev, - struct of_phandle_args *args) -{ - struct mt65xx_u3phy *u3phy = dev_get_drvdata(dev); - struct mt65xx_phy_instance *instance = NULL; - struct device_node *phy_np = args->np; - int index; - - if (args->args_count != 1) { - dev_err(dev, "invalid number of cells in 'phy' property\n"); - return ERR_PTR(-EINVAL); - } - - for (index = 0; index < u3phy->nphys; index++) - if (phy_np == u3phy->phys[index]->phy->dev.of_node) { - instance = u3phy->phys[index]; - break; - } - - if (!instance) { - dev_err(dev, "failed to find appropriate phy\n"); - return ERR_PTR(-EINVAL); - } - - instance->type = args->args[0]; - if (!(instance->type == PHY_TYPE_USB2 || - instance->type == PHY_TYPE_USB3 || - instance->type == PHY_TYPE_PCIE || - instance->type == PHY_TYPE_SATA)) { - dev_err(dev, "unsupported device type: %d\n", instance->type); - return ERR_PTR(-EINVAL); - } - - if (u3phy->pdata->version == MT_PHY_V1) { - phy_v1_banks_init(u3phy, instance); - } else if (u3phy->pdata->version == MT_PHY_V2) { - phy_v2_banks_init(u3phy, instance); - } else { - dev_err(dev, "phy version is not supported\n"); - return ERR_PTR(-EINVAL); - } - - return instance->phy; -} - -static const struct phy_ops mt65xx_u3phy_ops = { - .init = mt65xx_phy_init, - .exit = mt65xx_phy_exit, - .power_on = mt65xx_phy_power_on, - .power_off = mt65xx_phy_power_off, - .owner = THIS_MODULE, -}; - -static const struct mt65xx_phy_pdata tphy_v1_pdata = { - .avoid_rx_sen_degradation = false, - .version = MT_PHY_V1, -}; - -static const struct mt65xx_phy_pdata tphy_v2_pdata = { - .avoid_rx_sen_degradation = false, - .version = MT_PHY_V2, -}; - -static const struct mt65xx_phy_pdata mt8173_pdata = { - .avoid_rx_sen_degradation = true, - .version = MT_PHY_V1, -}; - -static const struct of_device_id mt65xx_u3phy_id_table[] = { - { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, - { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, - { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, - { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, - { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, - { }, -}; -MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table); - -static int mt65xx_u3phy_probe(struct platform_device *pdev) -{ - const struct of_device_id *match; - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct device_node *child_np; - struct phy_provider *provider; - struct resource *sif_res; - struct mt65xx_u3phy *u3phy; - struct resource res; - int port, retval; - - match = of_match_node(mt65xx_u3phy_id_table, pdev->dev.of_node); - if (!match) - return -EINVAL; - - u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL); - if (!u3phy) - return -ENOMEM; - - u3phy->pdata = match->data; - u3phy->nphys = of_get_child_count(np); - u3phy->phys = devm_kcalloc(dev, u3phy->nphys, - sizeof(*u3phy->phys), GFP_KERNEL); - if (!u3phy->phys) - return -ENOMEM; - - u3phy->dev = dev; - platform_set_drvdata(pdev, u3phy); - - if (u3phy->pdata->version == MT_PHY_V1) { - /* get banks shared by multiple phys */ - sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - u3phy->sif_base = devm_ioremap_resource(dev, sif_res); - if (IS_ERR(u3phy->sif_base)) { - dev_err(dev, "failed to remap sif regs\n"); - return PTR_ERR(u3phy->sif_base); - } - } - - /* it's deprecated, make it optional for backward compatibility */ - u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref"); - if (IS_ERR(u3phy->u3phya_ref)) { - if (PTR_ERR(u3phy->u3phya_ref) == -EPROBE_DEFER) - return -EPROBE_DEFER; - - u3phy->u3phya_ref = NULL; - } - - port = 0; - for_each_child_of_node(np, child_np) { - struct mt65xx_phy_instance *instance; - struct phy *phy; - - instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); - if (!instance) { - retval = -ENOMEM; - goto put_child; - } - - u3phy->phys[port] = instance; - - phy = devm_phy_create(dev, child_np, &mt65xx_u3phy_ops); - if (IS_ERR(phy)) { - dev_err(dev, "failed to create phy\n"); - retval = PTR_ERR(phy); - goto put_child; - } - - retval = of_address_to_resource(child_np, 0, &res); - if (retval) { - dev_err(dev, "failed to get address resource(id-%d)\n", - port); - goto put_child; - } - - instance->port_base = devm_ioremap_resource(&phy->dev, &res); - if (IS_ERR(instance->port_base)) { - dev_err(dev, "failed to remap phy regs\n"); - retval = PTR_ERR(instance->port_base); - goto put_child; - } - - instance->phy = phy; - instance->index = port; - phy_set_drvdata(phy, instance); - port++; - - /* if deprecated clock is provided, ignore instance's one */ - if (u3phy->u3phya_ref) - continue; - - instance->ref_clk = devm_clk_get(&phy->dev, "ref"); - if (IS_ERR(instance->ref_clk)) { - dev_err(dev, "failed to get ref_clk(id-%d)\n", port); - retval = PTR_ERR(instance->ref_clk); - goto put_child; - } - } - - provider = devm_of_phy_provider_register(dev, mt65xx_phy_xlate); - - return PTR_ERR_OR_ZERO(provider); -put_child: - of_node_put(child_np); - return retval; -} - -static struct platform_driver mt65xx_u3phy_driver = { - .probe = mt65xx_u3phy_probe, - .driver = { - .name = "mt65xx-u3phy", - .of_match_table = mt65xx_u3phy_id_table, - }, -}; - -module_platform_driver(mt65xx_u3phy_driver); - -MODULE_AUTHOR("Chunfeng Yun "); -MODULE_DESCRIPTION("mt65xx USB PHY driver"); -MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From e0ed408260dbbb2d6235f2478e2b2778255089d2 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Wed, 9 Aug 2017 17:17:58 +0800 Subject: phy: samsung: use of_device_get_match_data() reduce the boilerplate code to get the specific data Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/samsung/phy-exynos-dp-video.c | 5 ++--- drivers/phy/samsung/phy-exynos5-usbdrd.c | 7 ++++--- drivers/phy/samsung/phy-samsung-usb2.c | 9 +++------ 3 files changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos-dp-video.c b/drivers/phy/samsung/phy-exynos-dp-video.c index bb3279dbf88c..2dd6dd1f37a8 100644 --- a/drivers/phy/samsung/phy-exynos-dp-video.c +++ b/drivers/phy/samsung/phy-exynos-dp-video.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -78,7 +79,6 @@ static int exynos_dp_video_phy_probe(struct platform_device *pdev) { struct exynos_dp_video_phy *state; struct device *dev = &pdev->dev; - const struct of_device_id *match; struct phy_provider *phy_provider; struct phy *phy; @@ -93,8 +93,7 @@ static int exynos_dp_video_phy_probe(struct platform_device *pdev) return PTR_ERR(state->regs); } - match = of_match_node(exynos_dp_video_phy_of_match, dev->of_node); - state->drvdata = match->data; + state->drvdata = of_device_get_match_data(dev); phy = devm_phy_create(dev, NULL, &exynos_dp_video_phy_ops); if (IS_ERR(phy)) { diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 7c41daa2c625..22c68f58b181 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -662,7 +663,6 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) struct exynos5_usbdrd_phy *phy_drd; struct phy_provider *phy_provider; struct resource *res; - const struct of_device_id *match; const struct exynos5_usbdrd_phy_drvdata *drv_data; struct regmap *reg_pmu; u32 pmu_offset; @@ -681,9 +681,10 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) if (IS_ERR(phy_drd->reg_phy)) return PTR_ERR(phy_drd->reg_phy); - match = of_match_node(exynos5_usbdrd_phy_of_match, pdev->dev.of_node); + drv_data = of_device_get_match_data(dev); + if (!drv_data) + return -EINVAL; - drv_data = match->data; phy_drd->drv_data = drv_data; ret = exynos5_usbdrd_phy_clk_handle(phy_drd); diff --git a/drivers/phy/samsung/phy-samsung-usb2.c b/drivers/phy/samsung/phy-samsung-usb2.c index 1d22d93b552d..ea818866985a 100644 --- a/drivers/phy/samsung/phy-samsung-usb2.c +++ b/drivers/phy/samsung/phy-samsung-usb2.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -142,7 +143,6 @@ MODULE_DEVICE_TABLE(of, samsung_usb2_phy_of_match); static int samsung_usb2_phy_probe(struct platform_device *pdev) { - const struct of_device_id *match; const struct samsung_usb2_phy_config *cfg; struct device *dev = &pdev->dev; struct phy_provider *phy_provider; @@ -155,12 +155,9 @@ static int samsung_usb2_phy_probe(struct platform_device *pdev) return -EINVAL; } - match = of_match_node(samsung_usb2_phy_of_match, pdev->dev.of_node); - if (!match) { - dev_err(dev, "of_match_node() failed\n"); + cfg = of_device_get_match_data(dev); + if (!cfg) return -EINVAL; - } - cfg = match->data; drv = devm_kzalloc(dev, sizeof(struct samsung_usb2_phy_driver) + cfg->num_phys * sizeof(struct samsung_usb2_phy_instance), -- cgit v1.2.3 From 1cc81efe8e64ddea7af0607f59df9fd5ba163c81 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 17 Aug 2017 11:33:23 +0100 Subject: dt-bindings: phy: Add bindings for ralink-usb PHY Add a binding for the USB phy on Mediatek/Ralink SoCs. Signed-off-by: John Crispin Signed-off-by: Harvey Hunt Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/ralink-usb-phy.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt new file mode 100644 index 000000000000..9d2868a437ab --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt @@ -0,0 +1,23 @@ +Mediatek/Ralink USB PHY + +Required properties: + - compatible: "ralink,rt3352-usbphy" + "mediatek,mt7620-usbphy" + "mediatek,mt7628-usbphy" + - reg: required for "mediatek,mt7628-usbphy", unused otherwise + - #phy-cells: should be 0 + - ralink,sysctl: a phandle to a ralink syscon register region + - resets: the two reset controllers for host and device + - reset-names: the names of the 2 reset controllers + +Example: + +usbphy: phy { + compatible = "mediatek,mt7628-usbphy"; + reg = <0x10120000 0x1000>; + #phy-cells = <0>; + + ralink,sysctl = <&sysc>; + resets = <&rstctrl 22 &rstctrl 25>; + reset-names = "host", "device"; +}; -- cgit v1.2.3 From 2411a736ff09d349b0d4630ee5ff8a38d852ce3c Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 17 Aug 2017 11:33:22 +0100 Subject: phy: ralink-usb: add driver for Mediatek/Ralink Add a driver to setup the USB phy on Mediatek/Ralink SoCs. The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. Signed-off-by: John Crispin Signed-off-by: Harvey Hunt Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/ralink/Kconfig | 11 ++ drivers/phy/ralink/Makefile | 1 + drivers/phy/ralink/phy-ralink-usb.c | 249 ++++++++++++++++++++++++++++++++++++ 5 files changed, 263 insertions(+) create mode 100644 drivers/phy/ralink/Kconfig create mode 100644 drivers/phy/ralink/Makefile create mode 100644 drivers/phy/ralink/phy-ralink-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index d16704e77e68..441912c10b82 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -48,6 +48,7 @@ source "drivers/phy/marvell/Kconfig" source "drivers/phy/mediatek/Kconfig" source "drivers/phy/motorola/Kconfig" source "drivers/phy/qualcomm/Kconfig" +source "drivers/phy/ralink/Kconfig" source "drivers/phy/renesas/Kconfig" source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 1c68189b2894..06f3c500030d 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -18,6 +18,7 @@ obj-y += broadcom/ \ marvell/ \ motorola/ \ qualcomm/ \ + ralink/ \ samsung/ \ st/ \ ti/ diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig new file mode 100644 index 000000000000..b17635b407bc --- /dev/null +++ b/drivers/phy/ralink/Kconfig @@ -0,0 +1,11 @@ +# +# PHY drivers for Ralink platforms. +# +config PHY_RALINK_USB + tristate "Ralink USB PHY driver" + depends on RALINK || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + This option enables support for the Ralink USB PHY found inside + RT3352, MT7620, MT7628 and MT7688. diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile new file mode 100644 index 000000000000..5c9e326e8757 --- /dev/null +++ b/drivers/phy/ralink/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o diff --git a/drivers/phy/ralink/phy-ralink-usb.c b/drivers/phy/ralink/phy-ralink-usb.c new file mode 100644 index 000000000000..d19088c0ce5c --- /dev/null +++ b/drivers/phy/ralink/phy-ralink-usb.c @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2017 John Crispin + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RT_SYSC_REG_SYSCFG1 0x014 +#define RT_SYSC_REG_CLKCFG1 0x030 +#define RT_SYSC_REG_USB_PHY_CFG 0x05c + +#define OFS_U2_PHY_AC0 0x800 +#define OFS_U2_PHY_AC1 0x804 +#define OFS_U2_PHY_AC2 0x808 +#define OFS_U2_PHY_ACR0 0x810 +#define OFS_U2_PHY_ACR1 0x814 +#define OFS_U2_PHY_ACR2 0x818 +#define OFS_U2_PHY_ACR3 0x81C +#define OFS_U2_PHY_ACR4 0x820 +#define OFS_U2_PHY_AMON0 0x824 +#define OFS_U2_PHY_DCR0 0x860 +#define OFS_U2_PHY_DCR1 0x864 +#define OFS_U2_PHY_DTM0 0x868 +#define OFS_U2_PHY_DTM1 0x86C + +#define RT_RSTCTRL_UDEV BIT(25) +#define RT_RSTCTRL_UHST BIT(22) +#define RT_SYSCFG1_USB0_HOST_MODE BIT(10) + +#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25) +#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22) +#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20) +#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18) + +#define USB_PHY_UTMI_8B60M BIT(1) +#define UDEV_WAKEUP BIT(0) + +struct ralink_usb_phy { + struct reset_control *rstdev; + struct reset_control *rsthost; + u32 clk; + struct phy *phy; + void __iomem *base; + struct regmap *sysctl; +}; + +static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) +{ + writel(val, phy->base + reg); +} + +static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) +{ + return readl(phy->base + reg); +} + +static void ralink_usb_phy_init(struct ralink_usb_phy *phy) +{ + u2_phy_r32(phy, OFS_U2_PHY_AC2); + u2_phy_r32(phy, OFS_U2_PHY_ACR0); + u2_phy_r32(phy, OFS_U2_PHY_DCR0); + + u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0); + u2_phy_r32(phy, OFS_U2_PHY_DCR0); + u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0); + u2_phy_r32(phy, OFS_U2_PHY_DCR0); + u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0); + u2_phy_r32(phy, OFS_U2_PHY_DCR0); + u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0); + u2_phy_r32(phy, OFS_U2_PHY_DCR0); + u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0); + u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1); + u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3); + u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0); +} + +static int ralink_usb_phy_power_on(struct phy *_phy) +{ + struct ralink_usb_phy *phy = phy_get_drvdata(_phy); + u32 t; + + /* enable the phy */ + regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, + phy->clk, phy->clk); + + /* setup host mode */ + regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, + RT_SYSCFG1_USB0_HOST_MODE, + RT_SYSCFG1_USB0_HOST_MODE); + + /* deassert the reset lines */ + reset_control_deassert(phy->rsthost); + reset_control_deassert(phy->rstdev); + + /* + * The SDK kernel had a delay of 100ms. however on device + * testing showed that 10ms is enough + */ + mdelay(10); + + if (phy->base) + ralink_usb_phy_init(phy); + + /* print some status info */ + regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t); + dev_info(&phy->phy->dev, "remote usb device wakeup %s\n", + (t & UDEV_WAKEUP) ? ("enabled") : ("disabled")); + if (t & USB_PHY_UTMI_8B60M) + dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n"); + else + dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n"); + + return 0; +} + +static int ralink_usb_phy_power_off(struct phy *_phy) +{ + struct ralink_usb_phy *phy = phy_get_drvdata(_phy); + + /* disable the phy */ + regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, + phy->clk, 0); + + /* assert the reset lines */ + reset_control_assert(phy->rstdev); + reset_control_assert(phy->rsthost); + + return 0; +} + +static struct phy_ops ralink_usb_phy_ops = { + .power_on = ralink_usb_phy_power_on, + .power_off = ralink_usb_phy_power_off, + .owner = THIS_MODULE, +}; + +static const struct of_device_id ralink_usb_phy_of_match[] = { + { + .compatible = "ralink,rt3352-usbphy", + .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | + RT_CLKCFG1_UPHY0_CLK_EN) + }, + { + .compatible = "mediatek,mt7620-usbphy", + .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | + MT7620_CLKCFG1_UPHY0_CLK_EN) + }, + { + .compatible = "mediatek,mt7628-usbphy", + .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | + MT7620_CLKCFG1_UPHY0_CLK_EN) }, + { }, +}; +MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match); + +static int ralink_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct phy_provider *phy_provider; + const struct of_device_id *match; + struct ralink_usb_phy *phy; + + match = of_match_device(ralink_usb_phy_of_match, &pdev->dev); + if (!match) + return -ENODEV; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->clk = (u32) match->data; + phy->base = NULL; + + phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl"); + if (IS_ERR(phy->sysctl)) { + dev_err(dev, "failed to get sysctl registers\n"); + return PTR_ERR(phy->sysctl); + } + + /* The MT7628 and MT7688 require extra setup of PHY registers. */ + if (of_device_is_compatible(dev->of_node, "mediatek,mt7628-usbphy")) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + phy->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(phy->base)) { + dev_err(dev, "failed to remap register memory\n"); + return PTR_ERR(phy->base); + } + } + + phy->rsthost = devm_reset_control_get(&pdev->dev, "host"); + if (IS_ERR(phy->rsthost)) { + dev_err(dev, "host reset is missing\n"); + return PTR_ERR(phy->rsthost); + } + + phy->rstdev = devm_reset_control_get(&pdev->dev, "device"); + if (IS_ERR(phy->rstdev)) { + dev_err(dev, "device reset is missing\n"); + return PTR_ERR(phy->rstdev); + } + + phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops); + if (IS_ERR(phy->phy)) { + dev_err(dev, "failed to create PHY\n"); + return PTR_ERR(phy->phy); + } + phy_set_drvdata(phy->phy, phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static struct platform_driver ralink_usb_phy_driver = { + .probe = ralink_usb_phy_probe, + .driver = { + .of_match_table = ralink_usb_phy_of_match, + .name = "ralink-usb-phy", + } +}; +module_platform_driver(ralink_usb_phy_driver); + +MODULE_DESCRIPTION("Ralink USB phy driver"); +MODULE_AUTHOR("John Crispin "); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 7a1de063028aeb766e19bdc4f37233fc1a586911 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:04 +0800 Subject: dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3 The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu regions, clocks, resets, and optional vbus properties. These were not described when the H3 compatible string was added. Fixes: 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC") Signed-off-by: Chen-Yu Tsai Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index 005bc22938ff..893dd01dfe64 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -17,18 +17,21 @@ Required properties: * "phy_ctrl" * "pmu0" for H3, V3s and A64 * "pmu1" - * "pmu2" for sun4i, sun6i or sun7i + * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3 + * "pmu3" for sun8i-h3 - #phy-cells : from the generic phy bindings, must be 1 - clocks : phandle + clock specifier for the phy clocks - clock-names : * "usb_phy" for sun4i, sun5i or sun7i * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i * "usb0_phy", "usb1_phy" for sun8i + * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3 - resets : a list of phandle + reset specifier pairs - reset-names : * "usb0_reset" * "usb1_reset" - * "usb2_reset" for sun4i, sun6i or sun7i + * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3 + * "usb3_reset" for sun8i-h3 Optional properties: - usb0_id_det-gpios : gpio phandle for reading the otg id pin value @@ -37,6 +40,7 @@ Optional properties: - usb0_vbus-supply : regulator phandle for controller usb0 vbus - usb1_vbus-supply : regulator phandle for controller usb1 vbus - usb2_vbus-supply : regulator phandle for controller usb2 vbus +- usb3_vbus-supply : regulator phandle for controller usb3 vbus Example: usbphy: phy@0x01c13400 { -- cgit v1.2.3 From 1af556464495006472aa0c023bee088d053112d5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:05 +0800 Subject: dt-bindings: phy: sun4i-usb-phy: Add compatible string for A83T The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC. Add a compatible string for it, and describe the needed properties. Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring Tested-by: Maxime Ripard Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index 893dd01dfe64..cbc7847dbf6c 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -9,6 +9,7 @@ Required properties: * allwinner,sun7i-a20-usb-phy * allwinner,sun8i-a23-usb-phy * allwinner,sun8i-a33-usb-phy + * allwinner,sun8i-a83t-usb-phy * allwinner,sun8i-h3-usb-phy * allwinner,sun8i-v3s-usb-phy * allwinner,sun50i-a64-usb-phy @@ -17,7 +18,7 @@ Required properties: * "phy_ctrl" * "pmu0" for H3, V3s and A64 * "pmu1" - * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3 + * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 * "pmu3" for sun8i-h3 - #phy-cells : from the generic phy bindings, must be 1 - clocks : phandle + clock specifier for the phy clocks @@ -25,12 +26,13 @@ Required properties: * "usb_phy" for sun4i, sun5i or sun7i * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i * "usb0_phy", "usb1_phy" for sun8i + * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3 - resets : a list of phandle + reset specifier pairs - reset-names : * "usb0_reset" * "usb1_reset" - * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3 + * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3 * "usb3_reset" for sun8i-h3 Optional properties: -- cgit v1.2.3 From f0152c58c68f94f86bee8d91c4e4835e0c43ada7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:06 +0800 Subject: phy: sun4i-usb: Support secondary clock for HSIC PHY On the Allwinner A83T SoC, the last USB PHY is an HSIC PHY. It requires two clocks instead of one. On all Allwinner SoCs that share the common USB PHY design supported by the phy-sun4i-usb driver, the first PHY is always tied to OTG, and there is at most one HSIC PHY, typically the last. In this patch we take advantage of these known constraints and store an index in the compatible-string-related config structure describing which PHY is HSIC, needing the extra hsic_12M clock. Signed-off-by: Chen-Yu Tsai Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/allwinner/phy-sun4i-usb.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 3bea17b9405a..d259fdc6d7df 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -107,6 +107,7 @@ enum sun4i_usb_phy_type { struct sun4i_usb_phy_cfg { int num_phys; + int hsic_index; enum sun4i_usb_phy_type type; u32 disc_thresh; u8 phyctl_offset; @@ -126,6 +127,7 @@ struct sun4i_usb_phy_data { struct regulator *vbus; struct reset_control *reset; struct clk *clk; + struct clk *clk2; bool regulator_on; int index; } phys[MAX_PHYS]; @@ -261,8 +263,15 @@ static int sun4i_usb_phy_init(struct phy *_phy) if (ret) return ret; + ret = clk_prepare_enable(phy->clk2); + if (ret) { + clk_disable_unprepare(phy->clk); + return ret; + } + ret = reset_control_deassert(phy->reset); if (ret) { + clk_disable_unprepare(phy->clk2); clk_disable_unprepare(phy->clk); return ret; } @@ -315,6 +324,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy) sun4i_usb_phy_passby(phy, 0); reset_control_assert(phy->reset); + clk_disable_unprepare(phy->clk2); clk_disable_unprepare(phy->clk); return 0; @@ -719,6 +729,17 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) return PTR_ERR(phy->clk); } + /* The first PHY is always tied to OTG, and never HSIC */ + if (data->cfg->hsic_index && i == data->cfg->hsic_index) { + /* HSIC needs secondary clock */ + snprintf(name, sizeof(name), "usb%d_hsic_12M", i); + phy->clk2 = devm_clk_get(dev, name); + if (IS_ERR(phy->clk2)) { + dev_err(dev, "failed to get clock %s\n", name); + return PTR_ERR(phy->clk2); + } + } + snprintf(name, sizeof(name), "usb%d_reset", i); phy->reset = devm_reset_control_get(dev, name); if (IS_ERR(phy->reset)) { -- cgit v1.2.3 From 4b63743cdb47281466cd591ce7a2ae2512b23078 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Aug 2017 16:14:07 +0800 Subject: phy: sun4i-usb: Support A83T USB PHYs The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC. The phy initialization procedure is very different from other SoCs, but the PMU bits are the same, with additional bits for HSIC. Signed-off-by: Chen-Yu Tsai Tested-by: Maxime Ripard Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/allwinner/phy-sun4i-usb.c | 66 ++++++++++++++++++++++++++++------- 1 file changed, 54 insertions(+), 12 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index d259fdc6d7df..1161e11fb3cf 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -87,6 +87,16 @@ #define PHY_DISCON_TH_SEL 0x2a #define PHY_SQUELCH_DETECT 0x3c +/* A83T specific control bits for PHY0 */ +#define PHY_CTL_VBUSVLDEXT BIT(5) +#define PHY_CTL_SIDDQ BIT(3) + +/* A83T specific control bits for PHY2 HSIC */ +#define SUNXI_EHCI_HS_FORCE BIT(20) +#define SUNXI_HSIC_CONNECT_DET BIT(17) +#define SUNXI_HSIC_CONNECT_INT BIT(16) +#define SUNXI_HSIC BIT(1) + #define MAX_PHYS 4 /* @@ -100,6 +110,7 @@ enum sun4i_usb_phy_type { sun4i_a10_phy, sun6i_a31_phy, sun8i_a33_phy, + sun8i_a83t_phy, sun8i_h3_phy, sun8i_v3s_phy, sun50i_a64_phy, @@ -234,6 +245,7 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data, static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable) { + struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy); u32 bits, reg_value; if (!phy->pmu) @@ -242,6 +254,11 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable) bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN | SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN; + /* A83T USB2 is HSIC */ + if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2) + bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT | + SUNXI_HSIC; + reg_value = readl(phy->pmu); if (enable) @@ -276,21 +293,30 @@ static int sun4i_usb_phy_init(struct phy *_phy) return ret; } - if (phy->pmu && data->cfg->enable_pmu_unk1) { - val = readl(phy->pmu + REG_PMU_UNK1); - writel(val & ~2, phy->pmu + REG_PMU_UNK1); - } + if (data->cfg->type == sun8i_a83t_phy) { + if (phy->index == 0) { + val = readl(data->base + data->cfg->phyctl_offset); + val |= PHY_CTL_VBUSVLDEXT; + val &= ~PHY_CTL_SIDDQ; + writel(val, data->base + data->cfg->phyctl_offset); + } + } else { + if (phy->pmu && data->cfg->enable_pmu_unk1) { + val = readl(phy->pmu + REG_PMU_UNK1); + writel(val & ~2, phy->pmu + REG_PMU_UNK1); + } - /* Enable USB 45 Ohm resistor calibration */ - if (phy->index == 0) - sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); + /* Enable USB 45 Ohm resistor calibration */ + if (phy->index == 0) + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); - /* Adjust PHY's magnitude and rate */ - sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); + /* Adjust PHY's magnitude and rate */ + sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); - /* Disconnect threshold adjustment */ - sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, - data->cfg->disc_thresh, 2); + /* Disconnect threshold adjustment */ + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, + data->cfg->disc_thresh, 2); + } sun4i_usb_phy_passby(phy, 1); @@ -316,6 +342,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy) struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); if (phy->index == 0) { + if (data->cfg->type == sun8i_a83t_phy) { + void __iomem *phyctl = data->base + + data->cfg->phyctl_offset; + + writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl); + } + /* Disable pull-ups */ sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0); sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0); @@ -868,6 +901,14 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { .enable_pmu_unk1 = false, }; +static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { + .num_phys = 3, + .hsic_index = 2, + .type = sun8i_a83t_phy, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, +}; + static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .num_phys = 4, .type = sun8i_h3_phy, @@ -904,6 +945,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg }, { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg }, { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg }, + { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg }, { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg }, { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", -- cgit v1.2.3 From 1543645c3119da117d4cc6fb664c74157e66f237 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 11 Aug 2017 16:07:47 +0800 Subject: phy: rockchip-inno-usb2: add support for rockchip,usbgrf property The registers of usb-phy are distributed in grf and usbgrf on some Rockchip SoCs (e.g RV1108), this patch add a new rockchip,usbgrf property to support this companion grf design. Signed-off-by: Frank Wang Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 109 +++++++++++++++++--------- 1 file changed, 71 insertions(+), 38 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 626883d9d176..fb593ccb22d6 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -202,6 +202,7 @@ struct rockchip_usb2phy_port { /** * struct rockchip_usb2phy: usb2.0 phy driver data. * @grf: General Register Files regmap. + * @usbgrf: USB General Register Files regmap. * @clk: clock struct of phy input clk. * @clk480m: clock struct of phy output clk. * @clk_hw: clock struct of phy output clk management. @@ -216,6 +217,7 @@ struct rockchip_usb2phy_port { struct rockchip_usb2phy { struct device *dev; struct regmap *grf; + struct regmap *usbgrf; struct clk *clk; struct clk *clk480m; struct clk_hw clk480m_hw; @@ -227,7 +229,12 @@ struct rockchip_usb2phy { struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; }; -static inline int property_enable(struct rockchip_usb2phy *rphy, +static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) +{ + return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf; +} + +static inline int property_enable(struct regmap *base, const struct usb2phy_reg *reg, bool en) { unsigned int val, mask, tmp; @@ -236,17 +243,17 @@ static inline int property_enable(struct rockchip_usb2phy *rphy, mask = GENMASK(reg->bitend, reg->bitstart); val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); - return regmap_write(rphy->grf, reg->offset, val); + return regmap_write(base, reg->offset, val); } -static inline bool property_enabled(struct rockchip_usb2phy *rphy, +static inline bool property_enabled(struct regmap *base, const struct usb2phy_reg *reg) { int ret; unsigned int tmp, orig; unsigned int mask = GENMASK(reg->bitend, reg->bitstart); - ret = regmap_read(rphy->grf, reg->offset, &orig); + ret = regmap_read(base, reg->offset, &orig); if (ret) return false; @@ -258,11 +265,12 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); int ret; /* turn on 480m clk output if it is off */ - if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) { - ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true); + if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { + ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); if (ret) return ret; @@ -277,17 +285,19 @@ static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); /* turn off 480m clk output */ - property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false); + property_enable(base, &rphy->phy_cfg->clkout_ctl, false); } static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); + struct regmap *base = get_reg_base(rphy); - return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl); + return property_enabled(base, &rphy->phy_cfg->clkout_ctl); } static unsigned long @@ -409,13 +419,13 @@ static int rockchip_usb2phy_init(struct phy *phy) if (rport->mode != USB_DR_MODE_HOST && rport->mode != USB_DR_MODE_UNKNOWN) { /* clear bvalid status and enable bvalid detect irq */ - ret = property_enable(rphy, + ret = property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true); if (ret) goto out; - ret = property_enable(rphy, + ret = property_enable(rphy->grf, &rport->port_cfg->bvalid_det_en, true); if (ret) @@ -429,11 +439,13 @@ static int rockchip_usb2phy_init(struct phy *phy) } } else if (rport->port_id == USB2PHY_PORT_HOST) { /* clear linestate and enable linestate detect irq */ - ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true); + ret = property_enable(rphy->grf, + &rport->port_cfg->ls_det_clr, true); if (ret) goto out; - ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true); + ret = property_enable(rphy->grf, + &rport->port_cfg->ls_det_en, true); if (ret) goto out; @@ -449,6 +461,7 @@ static int rockchip_usb2phy_power_on(struct phy *phy) { struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); + struct regmap *base = get_reg_base(rphy); int ret; dev_dbg(&rport->phy->dev, "port power on\n"); @@ -460,7 +473,7 @@ static int rockchip_usb2phy_power_on(struct phy *phy) if (ret) return ret; - ret = property_enable(rphy, &rport->port_cfg->phy_sus, false); + ret = property_enable(base, &rport->port_cfg->phy_sus, false); if (ret) return ret; @@ -475,6 +488,7 @@ static int rockchip_usb2phy_power_off(struct phy *phy) { struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); + struct regmap *base = get_reg_base(rphy); int ret; dev_dbg(&rport->phy->dev, "port power off\n"); @@ -482,7 +496,7 @@ static int rockchip_usb2phy_power_off(struct phy *phy) if (rport->suspended) return 0; - ret = property_enable(rphy, &rport->port_cfg->phy_sus, true); + ret = property_enable(base, &rport->port_cfg->phy_sus, true); if (ret) return ret; @@ -526,11 +540,11 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) bool vbus_attach, sch_work, notify_charger; if (rport->utmi_avalid) - vbus_attach = - property_enabled(rphy, &rport->port_cfg->utmi_avalid); + vbus_attach = property_enabled(rphy->grf, + &rport->port_cfg->utmi_avalid); else - vbus_attach = - property_enabled(rphy, &rport->port_cfg->utmi_bvalid); + vbus_attach = property_enabled(rphy->grf, + &rport->port_cfg->utmi_bvalid); sch_work = false; notify_charger = false; @@ -650,22 +664,28 @@ static const char *chg_to_string(enum power_supply_type chg_type) static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, bool en) { - property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); - property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en); + struct regmap *base = get_reg_base(rphy); + + property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); + property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); } static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, bool en) { - property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en); - property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en); + struct regmap *base = get_reg_base(rphy); + + property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); + property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); } static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, bool en) { - property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en); - property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en); + struct regmap *base = get_reg_base(rphy); + + property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); + property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); } #define CHG_DCD_POLL_TIME (100 * HZ / 1000) @@ -677,6 +697,7 @@ static void rockchip_chg_detect_work(struct work_struct *work) struct rockchip_usb2phy_port *rport = container_of(work, struct rockchip_usb2phy_port, chg_work.work); struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + struct regmap *base = get_reg_base(rphy); bool is_dcd, tmout, vout; unsigned long delay; @@ -687,7 +708,7 @@ static void rockchip_chg_detect_work(struct work_struct *work) if (!rport->suspended) rockchip_usb2phy_power_off(rport->phy); /* put the controller in non-driving mode */ - property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false); + property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); /* Start DCD processing stage 1 */ rockchip_chg_enable_dcd(rphy, true); rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; @@ -696,7 +717,8 @@ static void rockchip_chg_detect_work(struct work_struct *work) break; case USB_CHG_STATE_WAIT_FOR_DCD: /* get data contact detection status */ - is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det); + is_dcd = property_enabled(rphy->grf, + &rphy->phy_cfg->chg_det.dp_det); tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES; /* stage 2 */ if (is_dcd || tmout) { @@ -713,7 +735,8 @@ static void rockchip_chg_detect_work(struct work_struct *work) } break; case USB_CHG_STATE_DCD_DONE: - vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det); + vout = property_enabled(rphy->grf, + &rphy->phy_cfg->chg_det.cp_det); rockchip_chg_enable_primary_det(rphy, false); if (vout) { /* Voltage Source on DM, Probe on DP */ @@ -734,7 +757,8 @@ static void rockchip_chg_detect_work(struct work_struct *work) } break; case USB_CHG_STATE_PRIMARY_DONE: - vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det); + vout = property_enabled(rphy->grf, + &rphy->phy_cfg->chg_det.dcp_det); /* Turn off voltage source */ rockchip_chg_enable_secondary_det(rphy, false); if (vout) @@ -748,7 +772,7 @@ static void rockchip_chg_detect_work(struct work_struct *work) /* fall through */ case USB_CHG_STATE_DETECTED: /* put the controller in normal mode */ - property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true); + property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); dev_info(&rport->phy->dev, "charger = %s\n", chg_to_string(rphy->chg_type)); @@ -790,8 +814,7 @@ static void rockchip_usb2phy_sm_work(struct work_struct *work) if (ret < 0) goto next_schedule; - ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, - &uhd); + ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd); if (ret < 0) goto next_schedule; @@ -845,8 +868,8 @@ static void rockchip_usb2phy_sm_work(struct work_struct *work) * activate the linestate detection to get the next device * plug-in irq. */ - property_enable(rphy, &rport->port_cfg->ls_det_clr, true); - property_enable(rphy, &rport->port_cfg->ls_det_en, true); + property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); + property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true); /* * we don't need to rearm the delayed work when the phy port @@ -869,14 +892,14 @@ static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data) struct rockchip_usb2phy_port *rport = data; struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); - if (!property_enabled(rphy, &rport->port_cfg->ls_det_st)) + if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st)) return IRQ_NONE; mutex_lock(&rport->mutex); /* disable linestate detect irq and clear its status */ - property_enable(rphy, &rport->port_cfg->ls_det_en, false); - property_enable(rphy, &rport->port_cfg->ls_det_clr, true); + property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false); + property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); mutex_unlock(&rport->mutex); @@ -896,13 +919,13 @@ static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data) struct rockchip_usb2phy_port *rport = data; struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); - if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st)) + if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) return IRQ_NONE; mutex_lock(&rport->mutex); /* clear bvalid detect irq pending status */ - property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true); + property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true); mutex_unlock(&rport->mutex); @@ -1045,6 +1068,16 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) if (IS_ERR(rphy->grf)) return PTR_ERR(rphy->grf); + if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) { + rphy->usbgrf = + syscon_regmap_lookup_by_phandle(dev->of_node, + "rockchip,usbgrf"); + if (IS_ERR(rphy->usbgrf)) + return PTR_ERR(rphy->usbgrf); + } else { + rphy->usbgrf = NULL; + } + if (of_property_read_u32(np, "reg", ®)) { dev_err(dev, "the reg property is not assigned in %s node\n", np->name); -- cgit v1.2.3 From c7527e07f0550fa98a2a8190c30a1e5a6cab8f93 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 11 Aug 2017 16:07:48 +0800 Subject: dt-bindings: phy-rockchip-inno-usb2: add rockchip,usbgrf property Add rockchip,usbgrf property to support the registers of usb-phy that are distributed in grf and usbgrf on some special Rockchip SoCs (e.g RV1108). Signed-off-by: Frank Wang Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt index 84d59b0db8df..69041373e018 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt @@ -18,6 +18,10 @@ Optional properties: usb-phy output 480m and xin24m. Refer to clk/clock-bindings.txt for generic clock consumer properties. + - rockchip,usbgrf : phandle to the syscon managing the "usb general + register files". When set driver will request its + phandle as one companion-grf for some special SoCs + (e.g RV1108). Required nodes : a sub-node is required for each port the phy provides. The sub-node name is used to identify host or otg port, -- cgit v1.2.3 From 0983e2abc8334a0fec1e93a47e712708acaf5ad2 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 11 Aug 2017 16:07:49 +0800 Subject: phy: rockchip-inno-usb2: add support for otg-mux interrupt The otg-id/otg-bvalid/linestate interrupts are multiplexed together in otg-port on some Rockchip SoC (e.g RV1108), this patch add support for it. Signed-off-by: Frank Wang Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 63 +++++++++++++++++++++------ 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index fb593ccb22d6..22b7b02a1b55 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -172,6 +172,8 @@ struct rockchip_usb2phy_cfg { * @vbus_attached: otg device vbus status. * @bvalid_irq: IRQ number assigned for vbus valid rise detection. * @ls_irq: IRQ number assigned for linestate detection. + * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate + * irqs to one irq in otg-port. * @mutex: for register updating in sm_work. * @chg_work: charge detect work. * @otg_sm_work: OTG state machine work. @@ -189,6 +191,7 @@ struct rockchip_usb2phy_port { bool vbus_attached; int bvalid_irq; int ls_irq; + int otg_mux_irq; struct mutex mutex; struct delayed_work chg_work; struct delayed_work otg_sm_work; @@ -934,6 +937,17 @@ static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data) return IRQ_HANDLED; } +static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) +{ + struct rockchip_usb2phy_port *rport = data; + struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); + + if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) + return rockchip_usb2phy_bvalid_irq(irq, data); + else + return IRQ_NONE; +} + static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, struct rockchip_usb2phy_port *rport, struct device_node *child_np) @@ -1010,20 +1024,43 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, rport->utmi_avalid = of_property_read_bool(child_np, "rockchip,utmi-avalid"); - rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); - if (rport->bvalid_irq < 0) { - dev_err(rphy->dev, "no vbus valid irq provided\n"); - ret = rport->bvalid_irq; - goto out; - } + /* + * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate + * interrupts muxed together, so probe the otg-mux interrupt first, + * if not found, then look for the regular interrupts one by one. + */ + rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); + if (rport->otg_mux_irq > 0) { + ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, + NULL, + rockchip_usb2phy_otg_mux_irq, + IRQF_ONESHOT, + "rockchip_usb2phy_otg", + rport); + if (ret) { + dev_err(rphy->dev, + "failed to request otg-mux irq handle\n"); + goto out; + } + } else { + rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); + if (rport->bvalid_irq < 0) { + dev_err(rphy->dev, "no vbus valid irq provided\n"); + ret = rport->bvalid_irq; + goto out; + } - ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL, - rockchip_usb2phy_bvalid_irq, - IRQF_ONESHOT, - "rockchip_usb2phy_bvalid", rport); - if (ret) { - dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n"); - goto out; + ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, + NULL, + rockchip_usb2phy_bvalid_irq, + IRQF_ONESHOT, + "rockchip_usb2phy_bvalid", + rport); + if (ret) { + dev_err(rphy->dev, + "failed to request otg-bvalid irq handle\n"); + goto out; + } } if (!IS_ERR(rphy->edev)) { -- cgit v1.2.3 From 9c1712d5ce1b9009fdac453d785cf7bcddceadac Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 11 Aug 2017 16:07:50 +0800 Subject: dt-bindings: phy-rockchip-inno-usb2: add otg-mux interrupt Add otg-mux property to support multiplexed interrupt in otg-port on some Rockchip SoC (e.g RV1108). Signed-off-by: Frank Wang Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt index 69041373e018..68230b575674 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt @@ -32,10 +32,14 @@ Required nodes : a sub-node is required for each port the phy provides. Required properties (port (child) node): - #phy-cells : must be 0. See ./phy-bindings.txt for details. - interrupts : specify an interrupt for each entry in interrupt-names. - - interrupt-names : a list which shall be the following entries: + - interrupt-names : a list which should be one of the following cases: + Regular case: * "otg-id" : for the otg id interrupt. * "otg-bvalid" : for the otg vbus interrupt. * "linestate" : for the host/otg linestate interrupt. + Some SoCs use one interrupt with the above muxed together, so for these + * "otg-mux" : otg-port interrupt, which mux otg-id/otg-bvalid/linestate + to one. Optional properties: - phy-supply : phandle to a regulator that provides power to VBUS. -- cgit v1.2.3 From fc938810d950f4846eb05b9af5614677e05c5a65 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Fri, 11 Aug 2017 16:08:48 +0800 Subject: phy: rockchip-inno-usb2: add support of usb2-phy for rv1108 SoCs This adds support usb2-phy for rv1108 SoCs and amend phy Documentation. Signed-off-by: Frank Wang Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-rockchip-inno-usb2.txt | 1 + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 43 ++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt index 68230b575674..a67ef2a3874f 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt @@ -6,6 +6,7 @@ Required properties (phy (parent) node): * "rockchip,rk3328-usb2phy" * "rockchip,rk3366-usb2phy" * "rockchip,rk3399-usb2phy" + * "rockchip,rv1108-usb2phy" - reg : the address offset of grf for usb-phy configuration. - #clock-cells : should be 0. - clock-output-names : specify the 480m output clock name. diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 22b7b02a1b55..994cc1a08f50 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -1397,11 +1397,54 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { + { + .reg = 0x100, + .num_ports = 2, + .clkout_ctl = { 0x108, 4, 4, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, + .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, + .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, + .ls_det_en = { 0x0680, 2, 2, 0, 1 }, + .ls_det_st = { 0x0690, 2, 2, 0, 1 }, + .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, + .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, + .utmi_ls = { 0x0804, 13, 12, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0680, 4, 4, 0, 1 }, + .ls_det_st = { 0x0690, 4, 4, 0, 1 }, + .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, + .utmi_ls = { 0x0804, 9, 8, 0, 1 }, + .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } + } + }, + .chg_det = { + .opmode = { 0x0100, 3, 0, 5, 1 }, + .cp_det = { 0x0804, 1, 1, 0, 1 }, + .dcp_det = { 0x0804, 0, 0, 0, 1 }, + .dp_det = { 0x0804, 2, 2, 0, 1 }, + .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, + .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, + .idp_src_en = { 0x0108, 9, 9, 0, 1 }, + .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, + .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, + .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct of_device_id rockchip_usb2phy_dt_match[] = { { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs }, { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, + { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, {} }; MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match); -- cgit v1.2.3 From 5e39c6cf575f0539a3cac86aa066624d17d86816 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 3 Aug 2017 09:26:19 +0800 Subject: phy: rockchip-typec: remove unused dfp variable In order to silent the 'W=1' compile warning: drivers/phy/rockchip/phy-rockchip-typec.c: In function 'tcphy_get_mode': drivers/phy/rockchip/phy-rockchip-typec.c:625:7: warning: variable 'dfp' set but not used [-Wunused-but-set-variable] Cc: Chris Zhong Signed-off-by: Shawn Lin Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/rockchip/phy-rockchip-typec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 7cfb0f8995de..4d2c57f21d76 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -622,12 +622,11 @@ static int tcphy_get_mode(struct rockchip_typec_phy *tcphy) struct extcon_dev *edev = tcphy->extcon; union extcon_property_value property; unsigned int id; - bool dfp, ufp, dp; + bool ufp, dp; u8 mode; int ret; ufp = extcon_get_state(edev, EXTCON_USB); - dfp = extcon_get_state(edev, EXTCON_USB_HOST); dp = extcon_get_state(edev, EXTCON_DISP_DP); mode = MODE_DFP_USB; -- cgit v1.2.3 From df674efa32b522fc024d26b0a667a7985e8b87da Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 30 Jun 2017 11:01:47 +0300 Subject: phy: phy-twl4030-usb: silence an uninitialized variable warning The "check" variable isn't necessarily initialized when we print it out in the debugging messages. It's a pretty haphazard affair and it doesn't matter very much what we initialize "check" to. Signed-off-by: Dan Carpenter Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/ti/phy-twl4030-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-twl4030-usb.c b/drivers/phy/ti/phy-twl4030-usb.c index 2990b3965460..0e9013868188 100644 --- a/drivers/phy/ti/phy-twl4030-usb.c +++ b/drivers/phy/ti/phy-twl4030-usb.c @@ -185,7 +185,7 @@ struct twl4030_usb { static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl, u8 module, u8 data, u8 address) { - u8 check; + u8 check = 0xFF; if ((twl_i2c_write_u8(module, data, address) >= 0) && (twl_i2c_read_u8(module, &check, address) >= 0) && -- cgit v1.2.3 From aea430ee0c4228b00e4ad303ff63dec93285b3e8 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 28 Jun 2017 15:19:37 +0300 Subject: phy: cpcap-usb: remove a stray tab This line was indented further that it should have been. Signed-off-by: Dan Carpenter Acked-by: Tony Lindgren Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/motorola/phy-cpcap-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/motorola/phy-cpcap-usb.c b/drivers/phy/motorola/phy-cpcap-usb.c index 9b63efa5ae4d..accaaaccb662 100644 --- a/drivers/phy/motorola/phy-cpcap-usb.c +++ b/drivers/phy/motorola/phy-cpcap-usb.c @@ -506,7 +506,7 @@ static void cpcap_usb_init_optional_gpios(struct cpcap_phy_ddata *ddata) if (IS_ERR(ddata->gpio[i])) { dev_info(ddata->dev, "no mode change GPIO%i: %li\n", i, PTR_ERR(ddata->gpio[i])); - ddata->gpio[i] = NULL; + ddata->gpio[i] = NULL; } } } -- cgit v1.2.3 From d9c51f4c53ae2af03aa8bd001d46f21b0adcdab8 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 19 Jun 2017 13:56:05 +0300 Subject: phy: brcm-sata: fix a timeout test in init We want to timeout with try set to zero so this should be a pre-op instead of post-op. Signed-off-by: Dan Carpenter Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/broadcom/phy-brcm-sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/broadcom/phy-brcm-sata.c b/drivers/phy/broadcom/phy-brcm-sata.c index e6544c8b1ace..9d7f74fe3d7c 100644 --- a/drivers/phy/broadcom/phy-brcm-sata.c +++ b/drivers/phy/broadcom/phy-brcm-sata.c @@ -335,7 +335,7 @@ static int brcm_nsp_sata_init(struct brcm_sata_port *port) /* Wait for pll_seq_done bit */ try = 50; - while (try--) { + while (--try) { val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, BLOCK0_XGXSSTATUS); if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) -- cgit v1.2.3