From b8cd337c8e0330f4a29b3d1f69b7c73b324b1f8d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:04 +0100 Subject: ARM: orion: always use MULTI_IRQ_HANDLER As a preparation for multiplatform support, this enables the MULTI_IRQ_HANDLER code unconditionally on dove and orion5x, and introduces the respective code on mv78xx0, which did not have it so far. The classic entry-macro.S files are removed as they are now obsolete. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mv78xx0/include/mach/entry-macro.S | 41 ------------------------ arch/arm/mach-mv78xx0/irq.c | 33 +++++++++++++++++++ 2 files changed, 33 insertions(+), 41 deletions(-) delete mode 100644 arch/arm/mach-mv78xx0/include/mach/entry-macro.S (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S deleted file mode 100644 index 6b1f088e0597..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Marvell MV78xx0 platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IRQ_VIRT_BASE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - @ check low interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] - ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] - mov \irqnr, #31 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no low interrupts set, check high interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] - ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF] - mov \irqnr, #63 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no high interrupts set, check error interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF] - ldr \tmp, [\base, #IRQ_MASK_ERR_OFF] - mov \irqnr, #95 - ands \irqstat, \irqstat, \tmp - - @ find first active interrupt source -1001: clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 32073444024b..2453c33faccf 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,12 +24,44 @@ static int __initdata gpio0_irqs[4] = { IRQ_MV78XX0_GPIO_24_31, }; +static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE; + +static asmlinkage void +__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF); + if (stat) { + unsigned int hwirq = 64 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} + void __init mv78xx0_init_irq(void) { orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); + set_handle_irq(mv78xx0_legacy_handle_irq); + /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of -- cgit v1.2.3