From c95680e6f56d6bc345a7907c4d4bd985e875f2a7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 19 Mar 2014 12:14:18 +0000 Subject: ARM: l2c: prima2: remove cache size override The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King --- arch/arm/mach-prima2/l2x0.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) (limited to 'arch/arm/mach-prima2') diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c index 2db82742fb74..dbd837bdb7f7 100644 --- a/arch/arm/mach-prima2/l2x0.c +++ b/arch/arm/mach-prima2/l2x0.c @@ -11,21 +11,6 @@ #include #include -struct l2x0_aux { - u32 val; - u32 mask; -}; - -static const struct l2x0_aux prima2_l2x0_aux __initconst = { - .val = L2C_AUX_CTRL_WAY_SIZE(2), - .mask = 0, -}; - -static const struct l2x0_aux marco_l2x0_aux __initconst = { - .val = L2C_AUX_CTRL_WAY_SIZE(2) | L310_AUX_CTRL_ASSOCIATIVITY_16, - .mask = L2X0_AUX_CTRL_MASK, -}; - static const struct of_device_id sirf_l2x0_ids[] __initconst = { { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, }, { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, }, @@ -35,13 +20,10 @@ static const struct of_device_id sirf_l2x0_ids[] __initconst = { static int __init sirfsoc_l2x0_init(void) { struct device_node *np; - const struct l2x0_aux *aux; np = of_find_matching_node(NULL, sirf_l2x0_ids); - if (np) { - aux = of_match_node(sirf_l2x0_ids, np)->data; - return l2x0_of_init(aux->val, aux->mask); - } + if (np) + return l2x0_of_init(0, ~0); return 0; } -- cgit v1.2.3