From af89fd812b00a52c54a3b9b2290fae4d31c7be9a Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Wed, 16 Feb 2011 07:40:39 +0100 Subject: ARM: 6703/1: SPEAr: update clk API support - Add support for divisor per parent clock - Add ENABLED_ON_INIT feature in clk - Add clk_set_rate(), round_rate_index & clk_round_rate() - Simplify clk_recalc functions - Add/update clock definitions Reviewed-by: Stanley Miao Signed-off-by: Viresh Kumar Signed-off-by: shiraz hashim Signed-off-by: Rajeev Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/misc_regs.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-spear3xx/include/mach') diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 6c919e1f9c43..0b93347c0f11 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -63,8 +63,8 @@ #define GPT1_CLK_SHIFT 11 #define GPT2_CLK_SHIFT 12 #define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_MASK 0 -#define AUX_CLK_PLL1_MASK 1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 #define PERIP1_CLK_ENB (MISC_BASE + 0x02C) /* PERIP1_CLK_ENB register masks */ @@ -113,6 +113,7 @@ #define RAS3_CLK_SYNT (MISC_BASE + 0x074) #define RAS4_CLK_SYNT (MISC_BASE + 0x078) /* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 #define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_MASK 1 #define AUX_EQ1_SEL 0 -- cgit v1.2.3