From a5944195d00a359e28d6e093593609bcee37ed5e Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 6 May 2019 16:47:41 -0700 Subject: xtensa: implement initialize_cacheattr for MPU cores Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa LSP RM document. Coalesce adjacent regions with the same cacheattr. Update Kconfig help text. Signed-off-by: Max Filippov --- arch/xtensa/Kconfig | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'arch/xtensa/Kconfig') diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 4b9aafe766c5..f081751db229 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -256,12 +256,26 @@ config MEMMAP_CACHEATTR region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. - Cache attribute values are specific for the MMU type, so e.g. - for region protection MMUs: 2 is cache bypass, 4 is WB cached, - 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable, - bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass, - 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is - reserved). + Cache attribute values are specific for the MMU type. + For region protection MMUs: + 1: WT cached, + 2: cache bypass, + 4: WB cached, + f: illegal. + For ful MMU: + bit 0: executable, + bit 1: writable, + bits 2..3: + 0: cache bypass, + 1: WB cache, + 2: WT cache, + 3: special (c and e are illegal, f is reserved). + For MPU: + 0: illegal, + 1: WB cache, + 2: WB, no-write-allocate cache, + 3: WT cache, + 4: cache bypass. config KSEG_PADDR hex "Physical address of the KSEG mapping" -- cgit v1.2.3