From 85af88b8f7d606be8a9b89fcda61a5df28a2028d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 16 Feb 2023 16:20:19 +0100 Subject: clk: renesas: r8a77980: Add Z2 clock Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3H, which uses a fixed SYS-CPU divider. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/aad9eaa57acf65cbe43e4d374066a72d760d54d8.1676560357.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/renesas') diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index 6dc63eaf1155..bac92c606d0b 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -72,6 +72,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ + DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1), DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1), -- cgit v1.2.3