From 64afa89ff60844f561a8934f40f0ed93e37b6a8b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 24 Jan 2017 10:41:19 +0100 Subject: clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU In order to achieve all the rates asked by the GPU, we might need to change the parent frequency. Signed-off-by: Maxime Ripard Acked-by: Stephen Boyd Acked-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-a33.c') diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 0d513d2674cb..a7b3c08ed0e2 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -468,7 +468,7 @@ static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc", 0x180, 0, 4, 24, 3, BIT(31), 0); static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", - 0x1a0, 0, 3, BIT(31), 0); + 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); static const char * const ats_parents[] = { "osc24M", "pll-periph" }; static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents, -- cgit v1.2.3