From 2808801aab8a595b5bb66c43e2f8b3f3a025cf79 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 22 May 2018 11:05:40 +0800 Subject: gpio: mxc: add clock operation Some i.MX SoCs have GPIO clock gates in CCM CCGR, such as i.MX6SLL, need to enable clocks before accessing GPIO registers, add optional clock operation for GPIO driver. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Linus Walleij --- drivers/gpio/gpio-mxc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 11ec7228ab08..f4dc31d88a04 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -20,6 +20,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ +#include #include #include #include @@ -60,6 +61,7 @@ struct mxc_gpio_hwdata { struct mxc_gpio_port { struct list_head node; void __iomem *base; + struct clk *clk; int irq; int irq_high; struct irq_domain *domain; @@ -434,6 +436,17 @@ static int mxc_gpio_probe(struct platform_device *pdev) if (port->irq < 0) return port->irq; + /* the controller clock is optional */ + port->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(port->clk)) + port->clk = NULL; + + err = clk_prepare_enable(port->clk); + if (err) { + dev_err(&pdev->dev, "Unable to enable clock.\n"); + return err; + } + /* disable the interrupt and clear the status */ writel(0, port->base + GPIO_IMR); writel(~0, port->base + GPIO_ISR); @@ -502,6 +515,7 @@ static int mxc_gpio_probe(struct platform_device *pdev) out_irqdomain_remove: irq_domain_remove(port->domain); out_bgio: + clk_disable_unprepare(port->clk); dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); return err; } -- cgit v1.2.3