From 265280b99822e5562eb431b102f2ba773c7b2a0a Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Feb 2022 17:01:06 -0500 Subject: drm/amd/display: add CLKMGR changes for DCN32/321 Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by: Aurabindo Pillai Acked-by: Jerry Zuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index b5570aa8e39d..4dd461e6c14b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -125,6 +125,7 @@ struct nv_wm_range_entry { double pstate_latency_us; double sr_exit_time_us; double sr_enter_plus_exit_time_us; + double fclk_change_latency_us; } dml_input; }; @@ -142,6 +143,7 @@ struct clk_state_registers_and_bypass { uint32_t dprefclk; uint32_t dispclk; uint32_t dppclk; + uint32_t dtbclk; uint32_t dppclk_bypass; uint32_t dcfclk_bypass; -- cgit v1.2.3