From d3b9f39d8417ee2f2cd87b5e5410015ce6f78491 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 26 Jul 2019 11:04:39 -0500 Subject: drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display') diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 69e4d0d96c7f..38b3c89b2a59 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -630,9 +630,11 @@ static void dcn20_init_hw(struct dc *dc) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Power gate DSCs */ for (i = 0; i < res_pool->res_cap->num_dsc; i++) dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false); +#endif /* Blank pixel data with OPP DPG */ for (i = 0; i < dc->res_pool->timing_generator_count; i++) { -- cgit v1.2.3