From 7cc3bf3f08b5645d1d08439fea36e4148dc6d7d3 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Wed, 2 May 2018 14:52:26 +0200 Subject: gpu: ipu-csi: add rgb/bgr888 24bit support to mbus_code_to_bus_cfg The 24bit RGB format configuration is currently missing, we add it now. Signed-off-by: Michael Grzeschik Signed-off-by: Philipp Zabel --- drivers/gpu/ipu-v3/ipu-csi.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/ipu-v3') diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c index 5450a2db1219..813a3199aa84 100644 --- a/drivers/gpu/ipu-v3/ipu-csi.c +++ b/drivers/gpu/ipu-v3/ipu-csi.c @@ -247,6 +247,12 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code) cfg->mipi_dt = MIPI_DT_RGB555; cfg->data_width = IPU_CSI_DATA_WIDTH_8; break; + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_BGR888_1X24: + cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444; + cfg->mipi_dt = MIPI_DT_RGB888; + cfg->data_width = IPU_CSI_DATA_WIDTH_8; + break; case MEDIA_BUS_FMT_UYVY8_2X8: cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY; cfg->mipi_dt = MIPI_DT_YUV422; -- cgit v1.2.3 From d36d0e6309dd8137cf438cbb680e72eb63c81425 Mon Sep 17 00:00:00 2001 From: Enrico Scholz Date: Thu, 3 May 2018 18:29:36 +0200 Subject: gpu: ipu-v3: csi: pass back mbus_code_to_bus_cfg error codes mbus_code_to_bus_cfg() can fail on unknown mbus codes; pass back the error to the caller. Signed-off-by: Enrico Scholz Signed-off-by: Jan Luebbe [p.zabel@pengutronix.de - renamed rc to ret for consistency] Signed-off-by: Philipp Zabel --- drivers/gpu/ipu-v3/ipu-csi.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/ipu-v3') diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c index 813a3199aa84..27262748a549 100644 --- a/drivers/gpu/ipu-v3/ipu-csi.c +++ b/drivers/gpu/ipu-v3/ipu-csi.c @@ -324,13 +324,17 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code) /* * Fill a CSI bus config struct from mbus_config and mbus_framefmt. */ -static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, +static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, struct v4l2_mbus_config *mbus_cfg, struct v4l2_mbus_framefmt *mbus_fmt) { + int ret; + memset(csicfg, 0, sizeof(*csicfg)); - mbus_code_to_bus_cfg(csicfg, mbus_fmt->code); + ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code); + if (ret < 0) + return ret; switch (mbus_cfg->type) { case V4L2_MBUS_PARALLEL: @@ -362,6 +366,8 @@ static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, /* will never get here, keep compiler quiet */ break; } + + return 0; } int ipu_csi_init_interface(struct ipu_csi *csi, @@ -371,8 +377,11 @@ int ipu_csi_init_interface(struct ipu_csi *csi, struct ipu_csi_bus_config cfg; unsigned long flags; u32 width, height, data = 0; + int ret; - fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt); + ret = fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt); + if (ret < 0) + return ret; /* set default sensor frame width and height */ width = mbus_fmt->width; @@ -593,11 +602,14 @@ int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, struct ipu_csi_bus_config cfg; unsigned long flags; u32 temp; + int ret; if (vc > 3) return -EINVAL; - mbus_code_to_bus_cfg(&cfg, mbus_fmt->code); + ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code); + if (ret < 0) + return ret; spin_lock_irqsave(&csi->lock, flags); -- cgit v1.2.3 From 1e6a1495c66947b289de9ba92b569b62ce68a979 Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Thu, 3 May 2018 18:29:37 +0200 Subject: gpu: ipu-v3: csi: support RGB565 on parallel bus The CSI_SENS_CONF_DATA_FMT_RGB565 configuration only works for MIPI CSI-2 sources. On the parallel bus, we need to use bayer (generic) mode instead. To handle this difference, we pass the mbus_type to mbus_code_to_bus_cfg(). Signed-off-by: Jan Luebbe [p.zabel@pengutronix.de - renamed rc to ret for consistency] Signed-off-by: Philipp Zabel --- drivers/gpu/ipu-v3/ipu-csi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/ipu-v3') diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c index 27262748a549..954eefe144e2 100644 --- a/drivers/gpu/ipu-v3/ipu-csi.c +++ b/drivers/gpu/ipu-v3/ipu-csi.c @@ -224,14 +224,18 @@ static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk, * Find the CSI data format and data width for the given V4L2 media * bus pixel format code. */ -static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code) +static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code, + enum v4l2_mbus_type mbus_type) { switch (mbus_code) { case MEDIA_BUS_FMT_BGR565_2X8_BE: case MEDIA_BUS_FMT_BGR565_2X8_LE: case MEDIA_BUS_FMT_RGB565_2X8_BE: case MEDIA_BUS_FMT_RGB565_2X8_LE: - cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565; + if (mbus_type == V4L2_MBUS_CSI2) + cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565; + else + cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; cfg->mipi_dt = MIPI_DT_RGB565; cfg->data_width = IPU_CSI_DATA_WIDTH_8; break; @@ -332,7 +336,7 @@ static int fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg, memset(csicfg, 0, sizeof(*csicfg)); - ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code); + ret = mbus_code_to_bus_cfg(csicfg, mbus_fmt->code, mbus_cfg->type); if (ret < 0) return ret; @@ -607,7 +611,7 @@ int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, if (vc > 3) return -EINVAL; - ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code); + ret = mbus_code_to_bus_cfg(&cfg, mbus_fmt->code, V4L2_MBUS_CSI2); if (ret < 0) return ret; -- cgit v1.2.3 From 4e3c5d7e05be6c9c6de4f4da9116511428924997 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Fri, 1 Jun 2018 15:13:16 +0200 Subject: gpu: ipu-v3: Allow negative offsets for interlaced scanning The IPU also supports interlaced buffers that start with the bottom field. To achieve this, the the base address EBA has to be increased by a stride length and the interlace offset ILO has to be set to the negative stride. Signed-off-by: Philipp Zabel Signed-off-by: Steve Longerbeam --- drivers/gpu/ipu-v3/ipu-cpmem.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/ipu-v3') diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c index 9f2d9ec42add..125721a7f8b6 100644 --- a/drivers/gpu/ipu-v3/ipu-cpmem.c +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c @@ -269,9 +269,20 @@ EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset); void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride) { + u32 ilo, sly; + + if (stride < 0) { + stride = -stride; + ilo = 0x100000 - (stride / 8); + } else { + ilo = stride / 8; + } + + sly = (stride * 2) - 1; + ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1); - ipu_ch_param_write_field(ch, IPU_FIELD_ILO, stride / 8); - ipu_ch_param_write_field(ch, IPU_FIELD_SLY, (stride * 2) - 1); + ipu_ch_param_write_field(ch, IPU_FIELD_ILO, ilo); + ipu_ch_param_write_field(ch, IPU_FIELD_SLY, sly); }; EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan); -- cgit v1.2.3 From 5c41bb6071257ba668a2b8933a8654e69aea1cee Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 2 Aug 2018 10:40:33 +0200 Subject: gpu: ipu-v3: add support for XRGB32 and XBGR32 V4L2 pixel formats These should be used instead of the ill-defined deprecated RGB32 and BGR32 V4L2 pixel formats. Signed-off-by: Philipp Zabel --- drivers/gpu/ipu-v3/ipu-common.c | 4 ++++ drivers/gpu/ipu-v3/ipu-cpmem.c | 8 ++++++++ drivers/gpu/ipu-v3/ipu-image-convert.c | 6 ++++++ 3 files changed, 18 insertions(+) (limited to 'drivers/gpu/ipu-v3') diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index 48685cddbad1..66e9405faedc 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -122,6 +122,8 @@ enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) case V4L2_PIX_FMT_NV16: case V4L2_PIX_FMT_NV61: return IPUV3_COLORSPACE_YUV; + case V4L2_PIX_FMT_XRGB32: + case V4L2_PIX_FMT_XBGR32: case V4L2_PIX_FMT_RGB32: case V4L2_PIX_FMT_BGR32: case V4L2_PIX_FMT_RGB24: @@ -190,6 +192,8 @@ int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat) return (24 * pixel_stride) >> 3; case V4L2_PIX_FMT_BGR32: case V4L2_PIX_FMT_RGB32: + case V4L2_PIX_FMT_XBGR32: + case V4L2_PIX_FMT_XRGB32: return (32 * pixel_stride) >> 3; default: break; diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c index 125721a7f8b6..0f1155ea0fbd 100644 --- a/drivers/gpu/ipu-v3/ipu-cpmem.c +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c @@ -188,6 +188,12 @@ static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat) case V4L2_PIX_FMT_RGB32: /* R G B A <=> [32:0] A:B:G:R */ return DRM_FORMAT_XBGR8888; + case V4L2_PIX_FMT_XBGR32: + /* B G R X <=> [32:0] X:R:G:B */ + return DRM_FORMAT_XRGB8888; + case V4L2_PIX_FMT_XRGB32: + /* X R G B <=> [32:0] B:G:R:X */ + return DRM_FORMAT_BGRX8888; case V4L2_PIX_FMT_UYVY: return DRM_FORMAT_UYVY; case V4L2_PIX_FMT_YUYV: @@ -787,6 +793,8 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image) break; case V4L2_PIX_FMT_RGB32: case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_XRGB32: + case V4L2_PIX_FMT_XBGR32: offset = image->rect.left * 4 + image->rect.top * pix->bytesperline; break; diff --git a/drivers/gpu/ipu-v3/ipu-image-convert.c b/drivers/gpu/ipu-v3/ipu-image-convert.c index 524a717ab28e..f4081962784c 100644 --- a/drivers/gpu/ipu-v3/ipu-image-convert.c +++ b/drivers/gpu/ipu-v3/ipu-image-convert.c @@ -226,6 +226,12 @@ static const struct ipu_image_pixfmt image_convert_formats[] = { }, { .fourcc = V4L2_PIX_FMT_BGR32, .bpp = 32, + }, { + .fourcc = V4L2_PIX_FMT_XRGB32, + .bpp = 32, + }, { + .fourcc = V4L2_PIX_FMT_XBGR32, + .bpp = 32, }, { .fourcc = V4L2_PIX_FMT_YUYV, .bpp = 16, -- cgit v1.2.3 From 9f0ba3d92fe63fa72f88238d9dde47a38a7d8f40 Mon Sep 17 00:00:00 2001 From: Steve Longerbeam Date: Wed, 1 Aug 2018 12:12:17 -0700 Subject: gpu: ipu-v3: Fix U/V offset macros for planar 4:2:0 The U and V offset macros for planar 4:2:0 (U_OFFSET, V_OFFSET, and UV_OFFSET), are not correct. The height component to the offset was calculated as: (pix->width * y / 4) But this does not produce correct offsets for odd values of y (luma line #). The luma line # must be decimated by two to produce the correct U/V line #, so the correct formula is: (pix->width * (y / 2) / 2) Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel --- drivers/gpu/ipu-v3/ipu-cpmem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/ipu-v3') diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c index 9f2d9ec42add..e68e4734f052 100644 --- a/drivers/gpu/ipu-v3/ipu-cpmem.c +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c @@ -530,17 +530,17 @@ static const struct ipu_rgb def_bgra_16 = { #define Y_OFFSET(pix, x, y) ((x) + pix->width * (y)) #define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * (y) / 4) + (x) / 2) + (pix->width * ((y) / 2) / 2) + (x) / 2) #define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \ (pix->width * pix->height / 4) + \ - (pix->width * (y) / 4) + (x) / 2) + (pix->width * ((y) / 2) / 2) + (x) / 2) #define U2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ (pix->width * (y) / 2) + (x) / 2) #define V2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ (pix->width * pix->height / 2) + \ (pix->width * (y) / 2) + (x) / 2) #define UV_OFFSET(pix, x, y) ((pix->width * pix->height) + \ - (pix->width * (y) / 2) + (x)) + (pix->width * ((y) / 2)) + (x)) #define UV2_OFFSET(pix, x, y) ((pix->width * pix->height) + \ (pix->width * y) + (x)) -- cgit v1.2.3 From 2d87e6c1b99c402360fdfe19ce4f579ab2f96adf Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 21 Jun 2018 21:13:38 +0200 Subject: gpu: ipu-v3: default to id 0 on missing OF alias This is better than storing -ENODEV in the id number. This fixes SoCs with only one IPU that don't specify an IPU alias in the device tree. Signed-off-by: Philipp Zabel --- drivers/gpu/ipu-v3/ipu-common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/ipu-v3') diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index 48685cddbad1..c73bd003f845 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -1401,6 +1401,8 @@ static int ipu_probe(struct platform_device *pdev) return -ENODEV; ipu->id = of_alias_get_id(np, "ipu"); + if (ipu->id < 0) + ipu->id = 0; if (of_device_is_compatible(np, "fsl,imx6qp-ipu") && IS_ENABLED(CONFIG_DRM)) { -- cgit v1.2.3