From 317b56c9aa9b0b0f4fae738e27998901b7b3b51c Mon Sep 17 00:00:00 2001 From: Raviteja Narayanam Date: Thu, 2 Feb 2023 15:11:33 +0530 Subject: i2c: xiic: Add wait for FIFO empty in send_tx If the tx_half_empty interrupt comes first instead of tx_empty, STOP bit is generated even before all the bytes are transmitted out on the bus. STOP bit should be sent only after all the bytes in the FIFO are transmitted out of the FIFO. So wait until FIFO is empty before sending the STOP bit. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli Acked-by: Michal Simek Signed-off-by: Wolfram Sang --- drivers/i2c/busses/i2c-xiic.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/i2c/busses/i2c-xiic.c') diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index edc64b79e293..57084696429c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -436,6 +436,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) data |= XIIC_TX_DYN_STOP_MASK; } else { u8 cr; + int status; + + /* Wait till FIFO is empty so STOP is sent last */ + status = xiic_wait_tx_empty(i2c); + if (status) + return; + /* Write to CR to stop */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & -- cgit v1.2.3