From 5b32b1368ae532a2d06c931ba6356c39a9de63ac Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 28 Sep 2015 19:51:18 +0300 Subject: memory: pl172: correct MPMC peripheral ID register bits According to PL172 TRM read of bits [7:6] of MPMCPeriphID3 is undefined, so unmask them. Also the driver supports all currently present revisions of PL172, this allows to alleviate requirements to the revision version matched by the driver. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Joachim Eastwood --- drivers/memory/pl172.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/memory') diff --git a/drivers/memory/pl172.c b/drivers/memory/pl172.c index b2ef6072fbf4..95a4ad72c992 100644 --- a/drivers/memory/pl172.c +++ b/drivers/memory/pl172.c @@ -278,9 +278,10 @@ static int pl172_remove(struct amba_device *adev) } static const struct amba_id pl172_ids[] = { + /* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */ { - .id = 0x07341172, - .mask = 0xffffffff, + .id = 0x07041172, + .mask = 0x3f0fffff, }, { 0, 0 }, }; -- cgit v1.2.3 From b794df56cbb46e031c29922acb24617b72f8f5a7 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 28 Sep 2015 19:51:19 +0300 Subject: memory: pl172: add ARM PrimeCell PL175 MPMC support The change adds support of ARM PrimeCell PL175 MPMC, the controller is found on NXP LPC32xx SoC. PL175 MPMC is very similar to PL172 controller, so it is preferred to add its support into the existing driver. One of the differences between PL172 and PL175 is that the latter one supports up to 6 AHB ports, but still only 4 AHB ports can be assigned to a static memory device, also PL175 does not have write buffer enable control in static memory configuration register. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Joachim Eastwood --- drivers/memory/pl172.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers/memory') diff --git a/drivers/memory/pl172.c b/drivers/memory/pl172.c index 95a4ad72c992..cb6ebb8e3a80 100644 --- a/drivers/memory/pl172.c +++ b/drivers/memory/pl172.c @@ -118,7 +118,8 @@ static int pl172_setup_static(struct amba_device *adev, if (of_property_read_bool(np, "mpmc,extended-wait")) cfg |= MPMC_STATIC_CFG_EW; - if (of_property_read_bool(np, "mpmc,buffer-enable")) + if (amba_part(adev) == 0x172 && + of_property_read_bool(np, "mpmc,buffer-enable")) cfg |= MPMC_STATIC_CFG_B; if (of_property_read_bool(np, "mpmc,write-protect")) @@ -190,6 +191,7 @@ static int pl172_parse_cs_config(struct amba_device *adev, } static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"}; +static const char * const pl175_revisions[] = {"r1"}; static int pl172_probe(struct amba_device *adev, const struct amba_id *id) { @@ -202,6 +204,9 @@ static int pl172_probe(struct amba_device *adev, const struct amba_id *id) if (amba_part(adev) == 0x172) { if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions)) rev = pl172_revisions[amba_rev(adev)]; + } else if (amba_part(adev) == 0x175) { + if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions)) + rev = pl175_revisions[amba_rev(adev)]; } dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev); @@ -283,6 +288,11 @@ static const struct amba_id pl172_ids[] = { .id = 0x07041172, .mask = 0x3f0fffff, }, + /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */ + { + .id = 0x07041175, + .mask = 0x3f0fffff, + }, { 0, 0 }, }; MODULE_DEVICE_TABLE(amba, pl172_ids); -- cgit v1.2.3 From f6d77beefd159f8c36b28c60d89e1557438a077e Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 28 Sep 2015 19:51:20 +0300 Subject: memory: pl172: add ARM PrimeCell PL176 MPMC support The change adds support of ARM PrimeCell PL176 MPMC. Static memory configuration of PL175 MPMC is very similar to one found on PL172 and PL175 controllers, so it is preferred to add its support into the existing driver. The difference is that PL176 supports up to 10 slave ports (but only 4 of them may be connected to static memory devices), AHB master bus width cab be 64-bit wide, also NAND devices can be interfaced. Similar to PL175 contoller, PL176 has no write buffer enable control in static memory configuration register, the rest of static memory configuration bits (with exception of NAND) is the same. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Joachim Eastwood --- drivers/memory/pl172.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/memory') diff --git a/drivers/memory/pl172.c b/drivers/memory/pl172.c index cb6ebb8e3a80..ff57195b4e37 100644 --- a/drivers/memory/pl172.c +++ b/drivers/memory/pl172.c @@ -192,6 +192,7 @@ static int pl172_parse_cs_config(struct amba_device *adev, static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"}; static const char * const pl175_revisions[] = {"r1"}; +static const char * const pl176_revisions[] = {"r0"}; static int pl172_probe(struct amba_device *adev, const struct amba_id *id) { @@ -207,6 +208,9 @@ static int pl172_probe(struct amba_device *adev, const struct amba_id *id) } else if (amba_part(adev) == 0x175) { if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions)) rev = pl175_revisions[amba_rev(adev)]; + } else if (amba_part(adev) == 0x176) { + if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions)) + rev = pl176_revisions[amba_rev(adev)]; } dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev); @@ -293,6 +297,11 @@ static const struct amba_id pl172_ids[] = { .id = 0x07041175, .mask = 0x3f0fffff, }, + /* PrimeCell MPMC PL176 */ + { + .id = 0x89041176, + .mask = 0xff0fffff, + }, { 0, 0 }, }; MODULE_DEVICE_TABLE(amba, pl172_ids); -- cgit v1.2.3