From f40a1e3705be23e845fbeec66acf3a6582524145 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 24 Jan 2018 00:42:13 +0800 Subject: soc: imx: gpc: ARM power domain should be always-on ARM power domain does NOT support runtime off, always-on flag should be set to avoid incorrect power state in pm_genpd_summary: Before: root@imx6qpdlsolox:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary domain status slaves /device runtime status ---------------------------------------------------------------------- ARM off-0 After: root@imx6qpdlsolox:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary domain status slaves /device runtime status ---------------------------------------------------------------------- ARM on Signed-off-by: Anson Huang Reviewed-by: Lucas Stach Acked-by: Dong Aisheng Signed-off-by: Shawn Guo --- drivers/soc/imx/gpc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c index 53f7275d6cbd..6cafa9b60bc6 100644 --- a/drivers/soc/imx/gpc.c +++ b/drivers/soc/imx/gpc.c @@ -254,6 +254,7 @@ static struct imx_pm_domain imx_gpc_domains[] = { { .base = { .name = "ARM", + .flags = GENPD_FLAG_ALWAYS_ON, }, }, { .base = { -- cgit v1.2.3 From e17ee5f08b9849b9f80fadab96364121c6bdd207 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Wed, 7 Feb 2018 14:20:03 +0800 Subject: soc: rockchip: disable jtag switching for RK3228/RK3229 SoCs Disable IO function switching between sdmmc and jtag for RK3228 and RK3229 SoCs. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/grf.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c index 15e71fd6c513..dd81b87d79f0 100644 --- a/drivers/soc/rockchip/grf.c +++ b/drivers/soc/rockchip/grf.c @@ -43,6 +43,17 @@ static const struct rockchip_grf_info rk3036_grf __initconst = { .num_values = ARRAY_SIZE(rk3036_defaults), }; +#define RK3228_GRF_SOC_CON6 0x418 + +static const struct rockchip_grf_value rk3228_defaults[] __initconst = { + { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) }, +}; + +static const struct rockchip_grf_info rk3228_grf __initconst = { + .values = rk3228_defaults, + .num_values = ARRAY_SIZE(rk3228_defaults), +}; + #define RK3288_GRF_SOC_CON0 0x244 static const struct rockchip_grf_value rk3288_defaults[] __initconst = { @@ -91,6 +102,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = { { .compatible = "rockchip,rk3036-grf", .data = (void *)&rk3036_grf, + }, { + .compatible = "rockchip,rk3228-grf", + .data = (void *)&rk3228_grf, }, { .compatible = "rockchip,rk3288-grf", .data = (void *)&rk3288_grf, -- cgit v1.2.3 From 3a2ad7bd3151cc282f06d18948dfb7a0e1138fb2 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Thu, 21 Dec 2017 20:40:52 +0100 Subject: soc: amlogic: meson-gx-pwrc-vpu: don't print error message on probe deferral The error message may be misleading in case of probe deferral (happens on my Odroid-C2). Therefore don't print it in this case. Fixes: 75fcb5ca4b46 "soc: amlogic: add Meson GX VPU Domains driver" Signed-off-by: Heiner Kallweit Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c index 2bdeebc48901..3adb2f2ecefd 100644 --- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c +++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c @@ -184,7 +184,8 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev) rstc = devm_reset_control_array_get(&pdev->dev, false, false); if (IS_ERR(rstc)) { - dev_err(&pdev->dev, "failed to get reset lines\n"); + if (PTR_ERR(rstc) != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get reset lines\n"); return PTR_ERR(rstc); } -- cgit v1.2.3 From 87f88732d25e6175cb4faa8070658f604660d720 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Thu, 21 Dec 2017 20:41:02 +0100 Subject: soc: amlogic: meson-gx-pwrc-vpu: fix error on shutdown when domain is powered off When operating the system headless headless, the domain is never powered on, leaving the clocks disabled. The shutdown function then tries to disable the already disabled clocks, resulting in errors. Therefore call meson_gx_pwrc_vpu_power_off() only if domain is powered on. This patch fixes the described issue on my system (Odorid-C2). Fixes: 339cd0ea0822 "soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader" Signed-off-by: Heiner Kallweit Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c index 3adb2f2ecefd..6289965c42e9 100644 --- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c +++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c @@ -225,7 +225,11 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev) static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev) { - meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd); + bool powered_off; + + powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd); + if (!powered_off) + meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd); } static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = { -- cgit v1.2.3 From 82a759c91801d1f9851196d73516a504064e472c Mon Sep 17 00:00:00 2001 From: "weiyongjun (A)" Date: Wed, 10 Jan 2018 14:19:40 +0000 Subject: meson-mx-socinfo: Make local function meson_mx_socinfo_init() static Fixes the following sparse warnings: drivers/soc/amlogic/meson-mx-socinfo.c:107:12: warning: symbol 'meson_mx_socinfo_init' was not declared. Should it be static? Signed-off-by: Wei Yongjun Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/meson-mx-socinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-mx-socinfo.c b/drivers/soc/amlogic/meson-mx-socinfo.c index 7bfff5ff22a2..78f0f1aeca57 100644 --- a/drivers/soc/amlogic/meson-mx-socinfo.c +++ b/drivers/soc/amlogic/meson-mx-socinfo.c @@ -104,7 +104,7 @@ static const struct of_device_id meson_mx_socinfo_analog_top_ids[] = { { /* sentinel */ } }; -int __init meson_mx_socinfo_init(void) +static int __init meson_mx_socinfo_init(void) { struct soc_device_attribute *soc_dev_attr; struct soc_device *soc_dev; -- cgit v1.2.3 From 01517dfc819f003855c1893d9382581cafe2877b Mon Sep 17 00:00:00 2001 From: "weiyongjun (A)" Date: Wed, 10 Jan 2018 14:19:48 +0000 Subject: meson-gx-socinfo: make local function meson_gx_socinfo_init static Fixes the following sparse warnings: drivers/soc/amlogic/meson-gx-socinfo.c:100:12: warning: symbol 'meson_gx_socinfo_init' was not declared. Should it be static? Signed-off-by: Wei Yongjun Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/meson-gx-socinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c index f2d8c3c53ea4..ea091f1f7dae 100644 --- a/drivers/soc/amlogic/meson-gx-socinfo.c +++ b/drivers/soc/amlogic/meson-gx-socinfo.c @@ -97,7 +97,7 @@ static const char *socinfo_to_soc_id(u32 socinfo) return "Unknown"; } -int __init meson_gx_socinfo_init(void) +static int __init meson_gx_socinfo_init(void) { struct soc_device_attribute *soc_dev_attr; struct soc_device *soc_dev; -- cgit v1.2.3 From 7353c54620732797dcc3b4b1fc6f3cc0c0d9b6ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 30 Jan 2018 22:18:16 +0100 Subject: soc: samsung: pmu: Populate children syscon nodes The syscon poweroff and restart nodes logically belong to the Power Management Unit so populate possible children. This also requires providing compatibles for Exynos5410 and Exynos7 so the PMU device and its children will be instantiated for them as well. Just like Exynos5433, these chipsets are not yet supported by the PMU driver. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Tested-by: Marek Szyprowski --- drivers/soc/samsung/exynos-pmu.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index f56adbd9fb8b..d34ca201b8b7 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -84,11 +84,15 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos5250-pmu", .data = exynos_pmu_data_arm_ptr(exynos5250_pmu_data), + }, { + .compatible = "samsung,exynos5410-pmu", }, { .compatible = "samsung,exynos5420-pmu", .data = exynos_pmu_data_arm_ptr(exynos5420_pmu_data), }, { .compatible = "samsung,exynos5433-pmu", + }, { + .compatible = "samsung,exynos7-pmu", }, { /*sentinel*/ }, }; @@ -126,6 +130,9 @@ static int exynos_pmu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pmu_context); + if (devm_of_platform_populate(dev)) + dev_err(dev, "Error populating children, reboot and poweroff might not work properly\n"); + dev_dbg(dev, "Exynos PMU Driver probe done\n"); return 0; } -- cgit v1.2.3 From 6e61c891a0bbe3cede4157b4ecdfbd1617098b5a Mon Sep 17 00:00:00 2001 From: Xiao Yao Date: Thu, 18 Jan 2018 17:56:45 +0800 Subject: soc: rockchip: disable jtag switching for RK3128 SoCs Disable IO function switching between sdmmc and jtag for RK3128 SoCs. Signed-off-by: Xiao Yao Reviewed-by: Shawn Lin Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/grf.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c index dd81b87d79f0..96882ffde67e 100644 --- a/drivers/soc/rockchip/grf.c +++ b/drivers/soc/rockchip/grf.c @@ -43,6 +43,17 @@ static const struct rockchip_grf_info rk3036_grf __initconst = { .num_values = ARRAY_SIZE(rk3036_defaults), }; +#define RK3128_GRF_SOC_CON0 0x140 + +static const struct rockchip_grf_value rk3128_defaults[] __initconst = { + { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) }, +}; + +static const struct rockchip_grf_info rk3128_grf __initconst = { + .values = rk3128_defaults, + .num_values = ARRAY_SIZE(rk3128_defaults), +}; + #define RK3228_GRF_SOC_CON6 0x418 static const struct rockchip_grf_value rk3228_defaults[] __initconst = { @@ -102,6 +113,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = { { .compatible = "rockchip,rk3036-grf", .data = (void *)&rk3036_grf, + }, { + .compatible = "rockchip,rk3128-grf", + .data = (void *)&rk3128_grf, }, { .compatible = "rockchip,rk3228-grf", .data = (void *)&rk3228_grf, -- cgit v1.2.3 From d909072d0521a84e67fbe5cce602d7befffabf7e Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Wed, 28 Feb 2018 20:41:43 +0800 Subject: soc: rockchip: power-domain: use clk_bulk APIs Use clk_bulk APIs, and also add error handling for clk enable. Signed-off-by: Jeffy Chen Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/pm_domains.c | 90 ++++++++++++++++++--------------------- 1 file changed, 42 insertions(+), 48 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 5c342167b9db..ad96ddeaeb78 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -67,7 +67,7 @@ struct rockchip_pm_domain { struct regmap **qos_regmap; u32 *qos_save_regs[MAX_QOS_REGS_NUM]; int num_clks; - struct clk *clks[]; + struct clk_bulk_data *clks; }; struct rockchip_pmu { @@ -274,13 +274,18 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) { - int i; + struct rockchip_pmu *pmu = pd->pmu; + int ret; - mutex_lock(&pd->pmu->mutex); + mutex_lock(&pmu->mutex); if (rockchip_pmu_domain_is_on(pd) != power_on) { - for (i = 0; i < pd->num_clks; i++) - clk_enable(pd->clks[i]); + ret = clk_bulk_enable(pd->num_clks, pd->clks); + if (ret < 0) { + dev_err(pmu->dev, "failed to enable clocks\n"); + mutex_unlock(&pmu->mutex); + return ret; + } if (!power_on) { rockchip_pmu_save_qos(pd); @@ -298,11 +303,10 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) rockchip_pmu_restore_qos(pd); } - for (i = pd->num_clks - 1; i >= 0; i--) - clk_disable(pd->clks[i]); + clk_bulk_disable(pd->num_clks, pd->clks); } - mutex_unlock(&pd->pmu->mutex); + mutex_unlock(&pmu->mutex); return 0; } @@ -364,8 +368,6 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, const struct rockchip_domain_info *pd_info; struct rockchip_pm_domain *pd; struct device_node *qos_node; - struct clk *clk; - int clk_cnt; int i, j; u32 id; int error; @@ -391,41 +393,36 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, return -EINVAL; } - clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells"); - pd = devm_kzalloc(pmu->dev, - sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]), - GFP_KERNEL); + pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); if (!pd) return -ENOMEM; pd->info = pd_info; pd->pmu = pmu; - for (i = 0; i < clk_cnt; i++) { - clk = of_clk_get(node, i); - if (IS_ERR(clk)) { - error = PTR_ERR(clk); + pd->num_clks = of_count_phandle_with_args(node, "clocks", + "#clock-cells"); + + pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, sizeof(*pd->clks), + GFP_KERNEL); + if (!pd->clks) + return -ENOMEM; + + for (i = 0; i < pd->num_clks; i++) { + pd->clks[i].clk = of_clk_get(node, i); + if (IS_ERR(pd->clks[i].clk)) { + error = PTR_ERR(pd->clks[i].clk); dev_err(pmu->dev, "%s: failed to get clk at index %d: %d\n", node->name, i, error); - goto err_out; - } - - error = clk_prepare(clk); - if (error) { - dev_err(pmu->dev, - "%s: failed to prepare clk %pC (index %d): %d\n", - node->name, clk, i, error); - clk_put(clk); - goto err_out; + return error; } - - pd->clks[pd->num_clks++] = clk; - - dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n", - clk, node->name); } + error = clk_bulk_prepare(pd->num_clks, pd->clks); + if (error) + goto err_put_clocks; + pd->num_qos = of_count_phandle_with_args(node, "pm_qos", NULL); @@ -435,7 +432,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, GFP_KERNEL); if (!pd->qos_regmap) { error = -ENOMEM; - goto err_out; + goto err_unprepare_clocks; } for (j = 0; j < MAX_QOS_REGS_NUM; j++) { @@ -445,7 +442,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, GFP_KERNEL); if (!pd->qos_save_regs[j]) { error = -ENOMEM; - goto err_out; + goto err_unprepare_clocks; } } @@ -453,13 +450,13 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, qos_node = of_parse_phandle(node, "pm_qos", j); if (!qos_node) { error = -ENODEV; - goto err_out; + goto err_unprepare_clocks; } pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); if (IS_ERR(pd->qos_regmap[j])) { error = -ENODEV; of_node_put(qos_node); - goto err_out; + goto err_unprepare_clocks; } of_node_put(qos_node); } @@ -470,7 +467,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, dev_err(pmu->dev, "failed to power on domain '%s': %d\n", node->name, error); - goto err_out; + goto err_unprepare_clocks; } pd->genpd.name = node->name; @@ -486,17 +483,16 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, pmu->genpd_data.domains[id] = &pd->genpd; return 0; -err_out: - while (--i >= 0) { - clk_unprepare(pd->clks[i]); - clk_put(pd->clks[i]); - } +err_unprepare_clocks: + clk_bulk_unprepare(pd->num_clks, pd->clks); +err_put_clocks: + clk_bulk_put(pd->num_clks, pd->clks); return error; } static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd) { - int i, ret; + int ret; /* * We're in the error cleanup already, so we only complain, @@ -507,10 +503,8 @@ static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd) dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", pd->genpd.name, ret); - for (i = 0; i < pd->num_clks; i++) { - clk_unprepare(pd->clks[i]); - clk_put(pd->clks[i]); - } + clk_bulk_unprepare(pd->num_clks, pd->clks); + clk_bulk_put(pd->num_clks, pd->clks); /* protect the zeroing of pm->num_clks */ mutex_lock(&pd->pmu->mutex); -- cgit v1.2.3 From b1271993aa3855bda5073c6061a095fd6e6febc6 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Mon, 5 Mar 2018 17:17:22 +0800 Subject: soc: rockchip: power-domain: Add a sanity check on pd->num_clks The of_count_phandle_with_args() can fail and return error(for example, rk3399 pd_vio doesn't have clocks). That would break the pd probe. Add a sanity check on pd->num_clks to avoid that. Fixes: 65084121d59d ("soc: rockchip: power-domain: use clk_bulk APIs") Reported-by: Shawn Lin Signed-off-by: Jeffy Chen Tested-by: Shawn Lin Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/pm_domains.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index ad96ddeaeb78..53efc386b1ad 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -402,11 +402,16 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, pd->num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells"); - - pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, sizeof(*pd->clks), - GFP_KERNEL); - if (!pd->clks) - return -ENOMEM; + if (pd->num_clks > 0) { + pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, + sizeof(*pd->clks), GFP_KERNEL); + if (!pd->clks) + return -ENOMEM; + } else { + dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n", + node->name, pd->num_clks); + pd->num_clks = 0; + } for (i = 0; i < pd->num_clks; i++) { pd->clks[i].clk = of_clk_get(node, i); -- cgit v1.2.3 From 6f9ed07fde03870ec247dcaf244313fe32521545 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 20 Feb 2018 13:58:07 +0200 Subject: soc/tegra: Add Tegra194 SoC configuration option Add the configuration option to enable support for the Tegra194 system- on-chip. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/soc/tegra/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 89ebe22a3e27..fe4481676da6 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -104,6 +104,16 @@ config ARCH_TEGRA_186_SOC multi-format support, ISP for image capture processing and BPMP for power management. +config ARCH_TEGRA_194_SOC + bool "NVIDIA Tegra194 SoC" + select MAILBOX + select TEGRA_BPMP + select TEGRA_HSP_MBOX + select TEGRA_IVC + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegra194 SoC. + endif endif -- cgit v1.2.3 From 56327f54d95c05791fd01e59a9dc03e3a4eafd21 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 20 Feb 2018 13:58:08 +0200 Subject: soc/tegra: pmc: Add Tegra194 compatibility string The Tegra194 PMC is mostly compatible with Tegra186, including in all currently supported features. As such, add a new compatibility string but point to the existing Tegra186 SoC data for now. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index ce62a47a6647..a2df230bf51a 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1920,6 +1920,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { }; static const struct of_device_id tegra_pmc_match[] = { + { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, -- cgit v1.2.3 From a263394a096e3578eb8dd77039b961c84a7392e7 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Thu, 25 Jan 2018 16:00:13 +0200 Subject: soc/tegra: pmc: MBIST work around for Tegra210 Apply the memory built-in self test work around when ungating certain Tegra210 power domains. Signed-off-by: Peter De Schrijver Reviewed-by: Jon Hunter Tested-by: Jon Hunter Tested-by: Hector Martin Tested-by: Andre Heider Tested-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index a2df230bf51a..010fbc928cd3 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -153,6 +153,7 @@ struct tegra_pmc_soc { bool has_tsense_reset; bool has_gpu_clamps; + bool needs_mbist_war; const struct tegra_io_pad_soc *io_pads; unsigned int num_io_pads; @@ -396,6 +397,11 @@ static int tegra_powergate_reset_deassert(struct tegra_powergate *pg) return 0; } +int __weak tegra210_clk_handle_mbist_war(unsigned int id) +{ + return 0; +} + static int tegra_powergate_power_up(struct tegra_powergate *pg, bool disable_clocks) { @@ -431,6 +437,11 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, usleep_range(10, 20); + if (pg->pmc->soc->needs_mbist_war) + err = tegra210_clk_handle_mbist_war(pg->id); + if (err) + goto disable_clks; + if (disable_clocks) tegra_powergate_disable_clocks(pg); @@ -1815,6 +1826,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { .cpu_powergates = tegra210_cpu_powergates, .has_tsense_reset = true, .has_gpu_clamps = true, + .needs_mbist_war = true, .num_io_pads = ARRAY_SIZE(tegra210_io_pads), .io_pads = tegra210_io_pads, .regs = &tegra20_pmc_regs, -- cgit v1.2.3 From 507c655a06c8553a67122c371608b024b997b0e0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 12 Feb 2018 16:09:43 +0100 Subject: soc/tegra: pmc: Pass PMC to tegra_powergate_power_up() tegra_powergate_sequence_power_up() makes up a struct tegra_powergate from scratch in order to reuse the same code as used by the generic PM domain implementation. However, subsequent patches will need to access the struct tegra_pmc * embedded in the powergate structure, so we need to make sure we always pass it in. Tested-by: Hector Martin Tested-by: Andre Heider Tested-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 010fbc928cd3..0efdc4ec019f 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -599,6 +599,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, pg.num_clks = 1; pg.resets = &rst; pg.num_resets = 1; + pg.pmc = pmc; err = tegra_powergate_power_up(&pg, false); if (err) -- cgit v1.2.3 From fa65f8045137d061134c15233d35a089cc85b87e Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Feb 2018 17:37:23 -0800 Subject: soc: qcom: rmtfs-mem: Add support for assigning memory to remote On some platform the remote processor's memory map is not statically configured in TrustZone, so each memory region that is to be accessed by the remote needs a call into TrustZone to set up the remote's permissions. Implement this for the rmtfs memory driver, to give the modem on 8996 access to the shared file system buffers. Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- drivers/soc/qcom/Kconfig | 1 + drivers/soc/qcom/rmtfs_mem.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e050eb83341d..a993d19fa562 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -47,6 +47,7 @@ config QCOM_QMI_HELPERS config QCOM_RMTFS_MEM tristate "Qualcomm Remote Filesystem memory driver" depends on ARCH_QCOM + select QCOM_SCM help The Qualcomm remote filesystem memory driver is used for allocating and exposing regions of shared memory with remote processors for the diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c index 0a43b2e8906f..c8999e38b005 100644 --- a/drivers/soc/qcom/rmtfs_mem.c +++ b/drivers/soc/qcom/rmtfs_mem.c @@ -37,6 +37,8 @@ struct qcom_rmtfs_mem { phys_addr_t size; unsigned int client_id; + + unsigned int perms; }; static ssize_t qcom_rmtfs_mem_show(struct device *dev, @@ -151,9 +153,11 @@ static void qcom_rmtfs_mem_release_device(struct device *dev) static int qcom_rmtfs_mem_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; + struct qcom_scm_vmperm perms[2]; struct reserved_mem *rmem; struct qcom_rmtfs_mem *rmtfs_mem; u32 client_id; + u32 vmid; int ret; rmem = of_reserved_mem_lookup(node); @@ -204,10 +208,31 @@ static int qcom_rmtfs_mem_probe(struct platform_device *pdev) rmtfs_mem->dev.release = qcom_rmtfs_mem_release_device; + ret = of_property_read_u32(node, "qcom,vmid", &vmid); + if (ret < 0 && ret != -EINVAL) { + dev_err(&pdev->dev, "failed to parse qcom,vmid\n"); + goto remove_cdev; + } else if (!ret) { + perms[0].vmid = QCOM_SCM_VMID_HLOS; + perms[0].perm = QCOM_SCM_PERM_RW; + perms[1].vmid = vmid; + perms[1].perm = QCOM_SCM_PERM_RW; + + rmtfs_mem->perms = BIT(QCOM_SCM_VMID_HLOS); + ret = qcom_scm_assign_mem(rmtfs_mem->addr, rmtfs_mem->size, + &rmtfs_mem->perms, perms, 2); + if (ret < 0) { + dev_err(&pdev->dev, "assign memory failed\n"); + goto remove_cdev; + } + } + dev_set_drvdata(&pdev->dev, rmtfs_mem); return 0; +remove_cdev: + cdev_device_del(&rmtfs_mem->cdev, &rmtfs_mem->dev); put_device: put_device(&rmtfs_mem->dev); @@ -217,6 +242,15 @@ put_device: static int qcom_rmtfs_mem_remove(struct platform_device *pdev) { struct qcom_rmtfs_mem *rmtfs_mem = dev_get_drvdata(&pdev->dev); + struct qcom_scm_vmperm perm; + + if (rmtfs_mem->perms) { + perm.vmid = QCOM_SCM_VMID_HLOS; + perm.perm = QCOM_SCM_PERM_RW; + + qcom_scm_assign_mem(rmtfs_mem->addr, rmtfs_mem->size, + &rmtfs_mem->perms, &perm, 1); + } cdev_device_del(&rmtfs_mem->cdev, &rmtfs_mem->dev); put_device(&rmtfs_mem->dev); -- cgit v1.2.3 From 90c29ed7627b6b4aeb603ee197650173c8434512 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 27 Feb 2018 16:45:25 -0800 Subject: soc: qcom: wcnss_ctrl: Fix increment in NV upload hdr.len includes both the size of the header and the fragment, so using this when stepping through the firmware causes us to skip 16 bytes every chunk of 3072 bytes; causing only the first fragment to actually be valid data. Instead use fragment size steps through the firmware blob. Fixes: ea7a1f275cf0 ("soc: qcom: Introduce WCNSS_CTRL SMD client") Reported-by: Will Newton Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- drivers/soc/qcom/wcnss_ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/wcnss_ctrl.c b/drivers/soc/qcom/wcnss_ctrl.c index d008e5b82db4..df3ccb30bc2d 100644 --- a/drivers/soc/qcom/wcnss_ctrl.c +++ b/drivers/soc/qcom/wcnss_ctrl.c @@ -249,7 +249,7 @@ static int wcnss_download_nv(struct wcnss_ctrl *wcnss, bool *expect_cbc) /* Increment for next fragment */ req->seq++; - data += req->hdr.len; + data += NV_FRAGMENT_SIZE; left -= NV_FRAGMENT_SIZE; } while (left > 0); -- cgit v1.2.3 From c59c9c85e36aa09cfd901cc15a0d8d3772c18195 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 7 Feb 2018 18:22:49 +0800 Subject: soc: mediatek: avoid hardcoded value with bus_prot_mask use a meaningful definition for bus_prot_mask instead of just hardcoded for it. Signed-off-by: Sean Wang Reviewed-by: Ulf Hansson Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-scpsys.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 435ce5ec648a..5346f33dd70b 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -518,7 +518,8 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = SPM_CONN_PWR_CON, - .bus_prot_mask = 0x0104, + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | + MT2701_TOP_AXI_PROT_EN_CONN_S, .clk_id = {CLK_NONE}, .active_wakeup = true, }, @@ -528,7 +529,7 @@ static const struct scp_domain_data scp_domain_data_mt2701[] = { .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .clk_id = {CLK_MM}, - .bus_prot_mask = 0x0002, + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0, .active_wakeup = true, }, [MT2701_POWER_DOMAIN_MFG] = { -- cgit v1.2.3 From c932ba8c38ba59d430a6e1d9600c0b8c4a029cce Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 7 Feb 2018 18:22:50 +0800 Subject: soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC Add SCPSYS power domain driver for MT7623A SoC. The MT7623A's power domains are the subset of MT7623 SoC's ones. As MT7623 SoC has full features whereas MT7623A is being designed just for router applications. Thus, MT7623A doesn't include those power domains multimedia function belongs to. In order to avoid certain errors undoubtedly happening at registering those power domains on MT7623A SoC using the existing MT7623 SCPSYS driver, it's required to define another setup specifically for MT7623A SoC. Signed-off-by: Sean Wang Reviewed-by: Ulf Hansson Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-scpsys.c | 55 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 5346f33dd70b..fc55faa17867 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #define SPM_VDE_PWR_CON 0x0210 @@ -794,6 +795,47 @@ static const struct scp_domain_data scp_domain_data_mt7622[] = { }, }; +/* + * MT7623A power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt7623a[] = { + [MT7623A_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | + MT2701_TOP_AXI_PROT_EN_CONN_S, + .clk_id = {CLK_NONE}, + .active_wakeup = true, + }, + [MT7623A_POWER_DOMAIN_ETH] = { + .name = "eth", + .sta_mask = PWR_STATUS_ETH, + .ctl_offs = SPM_ETH_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_ETHIF}, + .active_wakeup = true, + }, + [MT7623A_POWER_DOMAIN_HIF] = { + .name = "hif", + .sta_mask = PWR_STATUS_HIF, + .ctl_offs = SPM_HIF_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .clk_id = {CLK_ETHIF}, + .active_wakeup = true, + }, + [MT7623A_POWER_DOMAIN_IFR_MSC] = { + .name = "ifr_msc", + .sta_mask = PWR_STATUS_IFR_MSC, + .ctl_offs = SPM_IFR_MSC_PWR_CON, + .clk_id = {CLK_NONE}, + .active_wakeup = true, + }, +}; + /* * MT8173 power domain support */ @@ -935,6 +977,16 @@ static const struct scp_soc_data mt7622_data = { .bus_prot_reg_update = true, }; +static const struct scp_soc_data mt7623a_data = { + .domains = scp_domain_data_mt7623a, + .num_domains = ARRAY_SIZE(scp_domain_data_mt7623a), + .regs = { + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + }, + .bus_prot_reg_update = true, +}; + static const struct scp_soc_data mt8173_data = { .domains = scp_domain_data_mt8173, .num_domains = ARRAY_SIZE(scp_domain_data_mt8173), @@ -964,6 +1016,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { }, { .compatible = "mediatek,mt7622-scpsys", .data = &mt7622_data, + }, { + .compatible = "mediatek,mt7623a-scpsys", + .data = &mt7623a_data, }, { .compatible = "mediatek,mt8173-scpsys", .data = &mt8173_data, -- cgit v1.2.3 From 73ce2ce129783813e1ebc37d2c757fe5e0fab1ef Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Fri, 9 Feb 2018 02:07:59 +0800 Subject: soc: mediatek: fix the mistaken pointer accessed when subdomains are added Fix the pointer to struct scp_subdomian not being moved forward when each sub-domain is expected to be iteratively added through pm_genpd_add_subdomain call. Cc: stable@vger.kernel.org Fixes: 53fddb1a66dd ("soc: mediatek: reduce code duplication of scpsys_probe across all SoCs") Reported-by: Weiyi Lu Signed-off-by: Sean Wang Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-scpsys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index fc55faa17867..9de801e9e0e0 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -1048,7 +1048,7 @@ static int scpsys_probe(struct platform_device *pdev) pd_data = &scp->pd_data; - for (i = 0, sd = soc->subdomains ; i < soc->num_subdomains ; i++) { + for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) { ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin], pd_data->domains[sd->subdomain]); if (ret && IS_ENABLED(CONFIG_PM)) -- cgit v1.2.3 From 9f9971266110add19b512f7b10a6d922e741368e Mon Sep 17 00:00:00 2001 From: "weiyi.lu@mediatek.com" Date: Mon, 12 Mar 2018 15:03:39 +0800 Subject: soc: mediatek: update power domain data of MT2712 1. split MFG power domain into MFG/MFG_SC1/MFG_SC2/MFG_SC3 according to MT2712 ECO design change 2. add subdomain support for MT2712 Signed-off-by: Weiyi Lu Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-scpsys.c | 42 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 9de801e9e0e0..d762a46d434f 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -666,12 +666,48 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = { .name = "mfg", .sta_mask = PWR_STATUS_MFG, .ctl_offs = SPM_MFG_PWR_CON, - .sram_pdn_bits = GENMASK(11, 8), - .sram_pdn_ack_bits = GENMASK(19, 16), + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(16, 16), .clk_id = {CLK_MFG}, .bus_prot_mask = BIT(14) | BIT(21) | BIT(23), .active_wakeup = true, }, + [MT2712_POWER_DOMAIN_MFG_SC1] = { + .name = "mfg_sc1", + .sta_mask = BIT(22), + .ctl_offs = 0x02c0, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(16, 16), + .clk_id = {CLK_NONE}, + .active_wakeup = true, + }, + [MT2712_POWER_DOMAIN_MFG_SC2] = { + .name = "mfg_sc2", + .sta_mask = BIT(23), + .ctl_offs = 0x02c4, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(16, 16), + .clk_id = {CLK_NONE}, + .active_wakeup = true, + }, + [MT2712_POWER_DOMAIN_MFG_SC3] = { + .name = "mfg_sc3", + .sta_mask = BIT(30), + .ctl_offs = 0x01f8, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(16, 16), + .clk_id = {CLK_NONE}, + .active_wakeup = true, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt2712[] = { + {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VDEC}, + {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VENC}, + {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_ISP}, + {MT2712_POWER_DOMAIN_MFG, MT2712_POWER_DOMAIN_MFG_SC1}, + {MT2712_POWER_DOMAIN_MFG_SC1, MT2712_POWER_DOMAIN_MFG_SC2}, + {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, }; /* @@ -948,6 +984,8 @@ static const struct scp_soc_data mt2701_data = { static const struct scp_soc_data mt2712_data = { .domains = scp_domain_data_mt2712, .num_domains = ARRAY_SIZE(scp_domain_data_mt2712), + .subdomains = scp_subdomain_mt2712, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712), .regs = { .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND -- cgit v1.2.3 From 4c817ccf73abaf7b06a2630e8352d82648c8bc70 Mon Sep 17 00:00:00 2001 From: Vivek Gautam Date: Wed, 19 Jul 2017 17:59:08 +0200 Subject: soc/tegra: pmc: Use the new reset APIs to manage reset controllers Make use of of_reset_control_array_get_exclusive() to manage an array of reset controllers available with the device. Cc: Jon Hunter Cc: Thierry Reding Signed-off-by: Vivek Gautam [p.zabel@pengutronix.de: switch to hidden reset control array] Signed-off-by: Philipp Zabel Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 92 ++++++++++--------------------------------------- 1 file changed, 18 insertions(+), 74 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 0efdc4ec019f..d9fcdb592b39 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -127,8 +127,7 @@ struct tegra_powergate { unsigned int id; struct clk **clks; unsigned int num_clks; - struct reset_control **resets; - unsigned int num_resets; + struct reset_control *reset; }; struct tegra_io_pad_soc { @@ -369,34 +368,6 @@ out: return err; } -static int tegra_powergate_reset_assert(struct tegra_powergate *pg) -{ - unsigned int i; - int err; - - for (i = 0; i < pg->num_resets; i++) { - err = reset_control_assert(pg->resets[i]); - if (err) - return err; - } - - return 0; -} - -static int tegra_powergate_reset_deassert(struct tegra_powergate *pg) -{ - unsigned int i; - int err; - - for (i = 0; i < pg->num_resets; i++) { - err = reset_control_deassert(pg->resets[i]); - if (err) - return err; - } - - return 0; -} - int __weak tegra210_clk_handle_mbist_war(unsigned int id) { return 0; @@ -407,7 +378,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, { int err; - err = tegra_powergate_reset_assert(pg); + err = reset_control_assert(pg->reset); if (err) return err; @@ -431,7 +402,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, usleep_range(10, 20); - err = tegra_powergate_reset_deassert(pg); + err = reset_control_deassert(pg->reset); if (err) goto powergate_off; @@ -467,7 +438,7 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) usleep_range(10, 20); - err = tegra_powergate_reset_assert(pg); + err = reset_control_assert(pg->reset); if (err) goto disable_clks; @@ -486,7 +457,7 @@ static int tegra_powergate_power_down(struct tegra_powergate *pg) assert_resets: tegra_powergate_enable_clocks(pg); usleep_range(10, 20); - tegra_powergate_reset_deassert(pg); + reset_control_deassert(pg->reset); usleep_range(10, 20); disable_clks: @@ -597,8 +568,7 @@ int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, pg.id = id; pg.clks = &clk; pg.num_clks = 1; - pg.resets = &rst; - pg.num_resets = 1; + pg.reset = rst; pg.pmc = pmc; err = tegra_powergate_power_up(&pg, false); @@ -787,45 +757,22 @@ err: static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, struct device_node *np, bool off) { - struct reset_control *rst; - unsigned int i, count; int err; - count = of_count_phandle_with_args(np, "resets", "#reset-cells"); - if (count == 0) - return -ENODEV; - - pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL); - if (!pg->resets) - return -ENOMEM; - - for (i = 0; i < count; i++) { - pg->resets[i] = of_reset_control_get_by_index(np, i); - if (IS_ERR(pg->resets[i])) { - err = PTR_ERR(pg->resets[i]); - goto error; - } - - if (off) - err = reset_control_assert(pg->resets[i]); - else - err = reset_control_deassert(pg->resets[i]); - - if (err) { - reset_control_put(pg->resets[i]); - goto error; - } + pg->reset = of_reset_control_array_get_exclusive(np); + if (IS_ERR(pg->reset)) { + err = PTR_ERR(pg->reset); + pr_err("failed to get device resets: %d\n", err); + return err; } - pg->num_resets = count; - - return 0; - -error: - while (i--) - reset_control_put(pg->resets[i]); + if (off) + err = reset_control_assert(pg->reset); + else + err = reset_control_deassert(pg->reset); - kfree(pg->resets); + if (err) + reset_control_put(pg->reset); return err; } @@ -917,10 +864,7 @@ remove_genpd: pm_genpd_remove(&pg->genpd); remove_resets: - while (pg->num_resets--) - reset_control_put(pg->resets[pg->num_resets]); - - kfree(pg->resets); + reset_control_put(pg->reset); remove_clks: while (pg->num_clks--) -- cgit v1.2.3 From f842c41adc044e4586dd232c6e889f9d46180fa8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 12 Mar 2018 12:17:40 +0100 Subject: amlogic: meson-gx-socinfo: Update soc ids Updates the Amlogic Meson SoCs IDs for the Armv8 based SoCs. It includes the new families and packages. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/meson-gx-socinfo.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c index ea091f1f7dae..37ea0a1c24c8 100644 --- a/drivers/soc/amlogic/meson-gx-socinfo.c +++ b/drivers/soc/amlogic/meson-gx-socinfo.c @@ -33,6 +33,10 @@ static const struct meson_gx_soc_id { { "GXL", 0x21 }, { "GXM", 0x22 }, { "TXL", 0x23 }, + { "TXLX", 0x24 }, + { "AXG", 0x25 }, + { "GXLX", 0x26 }, + { "TXHD", 0x27 }, }; static const struct meson_gx_package_id { @@ -41,12 +45,18 @@ static const struct meson_gx_package_id { unsigned int pack_id; } soc_packages[] = { { "S905", 0x1f, 0 }, + { "S905H", 0x1f, 0x13 }, { "S905M", 0x1f, 0x20 }, { "S905D", 0x21, 0 }, { "S905X", 0x21, 0x80 }, + { "S905W", 0x21, 0xa0 }, { "S905L", 0x21, 0xc0 }, { "S905M2", 0x21, 0xe0 }, { "S912", 0x22, 0 }, + { "962X", 0x24, 0x10 }, + { "962E", 0x24, 0x20 }, + { "A113X", 0x25, 0x37 }, + { "A113D", 0x25, 0x22 }, }; static inline unsigned int socinfo_to_major(u32 socinfo) -- cgit v1.2.3