From cfac7d6a70b41982c770838edd5c2a3b4dbe55e6 Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Thu, 22 Oct 2015 09:38:39 +0300 Subject: staging: sm750fb: remove '#if 1' conditionals The code enclosed in '#if 1' anyway gets compiled. Removing useless conditionals. Signed-off-by: Mike Rapoport Signed-off-by: Greg Kroah-Hartman --- drivers/staging/sm750fb/ddk750_chip.c | 13 +++++-------- drivers/staging/sm750fb/ddk750_mode.c | 3 +-- drivers/staging/sm750fb/sm750_hw.c | 3 +-- 3 files changed, 7 insertions(+), 12 deletions(-) (limited to 'drivers/staging/sm750fb') diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index bab3d91c70bf..069d6e57d7a7 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -60,11 +60,10 @@ static void setChipClock(unsigned int frequency) { pll_value_t pll; unsigned int ulActualMxClk; -#if 1 + /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ if (getChipType() == SM750LE) return; -#endif if (frequency) { /* @@ -88,11 +87,11 @@ static void setChipClock(unsigned int frequency) static void setMemoryClock(unsigned int frequency) { unsigned int ulReg, divisor; - #if 1 + /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ if (getChipType() == SM750LE) return; -#endif + if (frequency) { /* Set the frequency to the maximum frequency that the DDR Memory can take which is 336MHz. */ @@ -135,11 +134,11 @@ static void setMemoryClock(unsigned int frequency) static void setMasterClock(unsigned int frequency) { unsigned int ulReg, divisor; -#if 1 + /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ if (getChipType() == SM750LE) return; -#endif + if (frequency) { /* Set the frequency to the maximum frequency that the SM750 engine can run, which is about 190 MHz. */ @@ -332,13 +331,11 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) unsigned int tmpClock, ret; pllcalparam *xparm; -#if 1 if (getChipType() == SM750LE) { /* SM750LE don't have prgrammable PLL and M/N values to work on. Just return the requested clock. */ return request_orig; } -#endif ret = 0; mini_diff = ~0; diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c index 2399b175ade0..fa35926680ab 100644 --- a/drivers/staging/sm750fb/ddk750_mode.c +++ b/drivers/staging/sm750fb/ddk750_mode.c @@ -168,14 +168,13 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) */ POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); -#if 1 + while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg)) { cnt++; if (cnt > 1000) break; POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg); } -#endif } else { ret = -1; } diff --git a/drivers/staging/sm750fb/sm750_hw.c b/drivers/staging/sm750fb/sm750_hw.c index 92e194ddb15a..8a5a8978638e 100644 --- a/drivers/staging/sm750fb/sm750_hw.c +++ b/drivers/staging/sm750fb/sm750_hw.c @@ -276,7 +276,7 @@ int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc, ret = 0; par = container_of(crtc, struct lynxfb_par, crtc); share = par->share; -#if 1 + if (!share->accel_off) { /* set 2d engine pixel format according to mode bpp */ switch (var->bits_per_pixel) { @@ -293,7 +293,6 @@ int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc, } hw_set2dformat(&share->accel, fmt); } -#endif /* set timing */ modparm.pixel_clock = ps_to_hz(var->pixclock); -- cgit v1.2.3