From ec8c0446b6e2b67b5c8813eb517f4bf00efa99a9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 12 Dec 2006 17:14:57 +0000 Subject: [PATCH] Optimize D-cache alias handling on fork Virtually index, physically tagged cache architectures can get away without cache flushing when forking. This patch adds a new cache flushing function flush_cache_dup_mm(struct mm_struct *) which for the moment I've implemented to do the same thing on all architectures except on MIPS where it's a no-op. Signed-off-by: Ralf Baechle Signed-off-by: Linus Torvalds --- include/asm-arm/cacheflush.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-arm/cacheflush.h') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index f0845646aacb..378a3a2ce8d9 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -319,6 +319,8 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, unsigned long len, int write); #endif +#define flush_cache_dup_mm(mm) flush_cache_mm(mm) + /* * flush_cache_user_range is used when we want to ensure that the * Harvard caches are synchronised for the user space address range. -- cgit v1.2.3 From 1c9d3df5e88ad7db23f5b22f4341c39722a904a4 Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Sat, 30 Dec 2006 16:08:50 +0100 Subject: [ARM] 4078/1: Fix ARM copypage cache coherency problems If PG_dcache_dirty is set for a page, we need to flush the source page before performing any copypage operation using a different virtual address. This fixes the copypage implementations for XScale, StrongARM and ARMv6. This patch fixes segmentation faults seen in the dynamic linker under the usage patterns in glibc 2.4/2.5. Signed-off-by: Richard Purdie Signed-off-by: Russell King --- include/asm-arm/cacheflush.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-arm/cacheflush.h') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 378a3a2ce8d9..d51049522cd0 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -355,6 +355,8 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, */ extern void flush_dcache_page(struct page *); +extern void __flush_dcache_page(struct address_space *mapping, struct page *page); + #define flush_dcache_mmap_lock(mapping) \ write_lock_irq(&(mapping)->tree_lock) #define flush_dcache_mmap_unlock(mapping) \ -- cgit v1.2.3 From 6020dff09252e3670a89edb36baaa4afb9b10d15 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 30 Dec 2006 23:17:40 +0000 Subject: [ARM] Resolve fuse and direct-IO failures due to missing cache flushes fuse does not work on ARM due to cache incoherency issues - fuse wants to use get_user_pages() to copy data from the current process into kernel space. However, since this accesses userspace via the kernel mapping, the kernel mapping can be out of date wrt data written to userspace. This can lead to unpredictable behaviour (in the case of fuse) or data corruption for direct-IO. This resolves debian bug #402876 Signed-off-by: Russell King --- include/asm-arm/cacheflush.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/asm-arm/cacheflush.h') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index d51049522cd0..5f531ea03059 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -357,6 +357,16 @@ extern void flush_dcache_page(struct page *); extern void __flush_dcache_page(struct address_space *mapping, struct page *page); +#define ARCH_HAS_FLUSH_ANON_PAGE +static inline void flush_anon_page(struct vm_area_struct *vma, + struct page *page, unsigned long vmaddr) +{ + extern void __flush_anon_page(struct vm_area_struct *vma, + struct page *, unsigned long); + if (PageAnon(page)) + __flush_anon_page(vma, page, vmaddr); +} + #define flush_dcache_mmap_lock(mapping) \ write_lock_irq(&(mapping)->tree_lock) #define flush_dcache_mmap_unlock(mapping) \ -- cgit v1.2.3