From 4e382db36cf50969f6bafb1ac99ae6c3f5bf5568 Mon Sep 17 00:00:00 2001 From: Yetunde Adebisi Date: Tue, 5 Apr 2016 15:10:50 +0100 Subject: drm/dp: Add definition for Display Control DPCD Registers capability size This is used when reading Display Control capability Registers on the sink device. cc: dri-devel@lists.freedesktop.org Signed-off-by: Yetunde Adebisi Reviewed-by: Jani Nikula Acked-by: Dave Airlie Signed-off-by: Jani Nikula Link: http://patchwork.freedesktop.org/patch/msgid/1459865452-9138-2-git-send-email-yetundex.adebisi@intel.com --- include/drm/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/drm/drm_dp_helper.h') diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1252108da0ef..92d9a5258e6d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); -- cgit v1.2.3