From 7bdc072086939093238a970f054e8e63d531253d Mon Sep 17 00:00:00 2001 From: Yakir Yang Date: Wed, 29 Jun 2016 17:15:18 +0800 Subject: drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting As vendor document indicate, when REF_CLK bit set 0, then DP phy's REF_CLK should switch to 24M source clock. But due to IC PHY layout mistaken, some chips need to flip this bit(like RK3288), and unfortunately they didn't indicate in the DP version register. That's why we have to make this little hack. Signed-off-by: Yakir Yang Reviewed-by: Tomasz Figa Tested-by: Javier Martinez Canillas Reviewed-by: Sean Paul --- include/drm/bridge/analogix_dp.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/drm') diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h index 25afb31f0389..790ab5d07a88 100644 --- a/include/drm/bridge/analogix_dp.h +++ b/include/drm/bridge/analogix_dp.h @@ -18,6 +18,11 @@ enum analogix_dp_devtype { RK3288_DP, }; +static inline bool is_rockchip(enum analogix_dp_devtype type) +{ + return type == RK3288_DP; +} + struct analogix_dp_plat_data { enum analogix_dp_devtype dev_type; struct drm_panel *panel; -- cgit v1.2.3