From 5f82bfced6118450cb9ea3f12316568f6fac10ab Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:38 +0100 Subject: clk: imx6ul: fix enet1 gate configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the "i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root of PLL6. It is controlling ENET1 separately. So, instead of this picture (implementation before this patch): fec1 <- enet_ref (divider) <---------------------------, |- pll6_enet (gate) fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ we should have this one (after this patch): fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ With this fix, the RMII reference clock will be turned off, after setting network interface down on each separate interface (ip l s dev eth0 down). Which was not working before, on system with both FECs enabled. Signed-off-by: Oleksij Rempel Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de --- include/dt-bindings/clock/imx6ul-clock.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index 79094338e6f1..b44920f1edb0 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -256,7 +256,8 @@ #define IMX6UL_CLK_GPIO4 247 #define IMX6UL_CLK_GPIO5 248 #define IMX6UL_CLK_MMDC_P1_IPG 249 +#define IMX6UL_CLK_ENET1_REF_125M 250 -#define IMX6UL_CLK_END 250 +#define IMX6UL_CLK_END 251 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -- cgit v1.2.3