From a3c83ff20c64a0ea3580aa7ed2953ff1602334dd Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 19 May 2015 14:43:30 +0300 Subject: clk: tegra: Add DFLL DVCO reset control for Tegra124 The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Thanks to Aleksandr Frid for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley [ttynkkynen: ported to tegra124 from tegra114] Signed-off-by: Tuomas Tynkkynen [mikko.perttunen: ported to special reset callback] Signed-off-by: Mikko Perttunen Acked-by: Michael Turquette Signed-off-by: Thierry Reding --- include/dt-bindings/reset/tegra124-car.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/reset/tegra124-car.h (limited to 'include/dt-bindings/reset') diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h new file mode 100644 index 000000000000..070e4f6e7486 --- /dev/null +++ b/include/dt-bindings/reset/tegra124-car.h @@ -0,0 +1,12 @@ +/* + * This header provides Tegra124-specific constants for binding + * nvidia,tegra124-car. + */ + +#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H +#define _DT_BINDINGS_RESET_TEGRA124_CAR_H + +#define TEGRA124_RESET(x) (6 * 32 + (x)) +#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) + +#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ -- cgit v1.2.3