From 68a4f2caaa17ce62890c51ef957dd008c2e42aae Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 14 Oct 2020 01:19:30 -0500 Subject: ASoC: sun8i-codec: Correct the BCLK divisor calculation Previously, the BCLK divisor calculation assumed zero padding and exactly two slots. In order to support the TDM slot binding and 20/24-bit word sizes, those assumptions must be removed. Due to hardware limitations, the BCLK/LRCK ratio is not as simple as "slot_width * slots". However, the correct value is already calculated elsewhere in this function, since it must also be programmed into the hardware. Reuse that value to calculate the correct SYSCLK/BCLK divisor. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20201014061941.4306-7-samuel@sholland.org Signed-off-by: Mark Brown --- sound/soc/sunxi/sun8i-codec.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'sound/soc/sunxi/sun8i-codec.c') diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c index 92fcef45097d..ae885774c877 100644 --- a/sound/soc/sunxi/sun8i-codec.c +++ b/sound/soc/sunxi/sun8i-codec.c @@ -284,11 +284,11 @@ static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { }; static u8 sun8i_codec_get_bclk_div(struct sun8i_codec *scodec, - unsigned int rate, - unsigned int word_size) + unsigned int lrck_div_order, + unsigned int sample_rate) { unsigned long clk_rate = clk_get_rate(scodec->clk_module); - unsigned int div = clk_rate / rate / word_size / 2; + unsigned int div = clk_rate / sample_rate >> lrck_div_order; unsigned int best_val = 0, best_diff = ~0; int i; @@ -348,11 +348,6 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK, word_size << SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ); - bclk_div = sun8i_codec_get_bclk_div(scodec, params_rate(params), 16); - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, - SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, - bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); - /* LRCK divider (BCLK/LRCK ratio) */ lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width); if (lrck_div_order < 0) @@ -362,6 +357,12 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK, (lrck_div_order - 4) << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV); + /* BCLK divider (SYSCLK/BCLK ratio) */ + bclk_div = sun8i_codec_get_bclk_div(scodec, lrck_div_order, params_rate(params)); + regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL, + SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK, + bclk_div << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV); + sample_rate = sun8i_codec_get_hw_rate(params); if (sample_rate < 0) return sample_rate; -- cgit v1.2.3