From 6a53a5fbc8f494e69922e13491f7077ce010ec28 Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Thu, 17 Aug 2023 18:23:46 +0200 Subject: KVM: selftests: Add array order helpers to riscv get-reg-list Add a couple macros to use when filling arrays in order to ensure the elements are placed in the right order, regardless of the order we prefer to read them. And immediately apply the new macro to resorting the ISA extension lists alphabetically. Signed-off-by: Andrew Jones Reviewed-by: Haibo Xu Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 86 +++++++++++++----------- 1 file changed, 47 insertions(+), 39 deletions(-) (limited to 'tools') diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 9f99ea42f45f..a61b706a8778 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -25,6 +25,8 @@ bool filter_reg(__u64 reg) * the visibility of the ISA_EXT register itself. * * Based on above, we should filter-out all ISA_EXT registers. + * + * Note: The below list is alphabetically sorted. */ case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C: @@ -33,21 +35,21 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: - case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: return true; /* AIA registers are always available when Ssaia can't be disabled */ @@ -311,35 +313,38 @@ static const char *fp_d_id_to_str(const char *prefix, __u64 id) return NULL; } +#define KVM_ISA_EXT_ARR(ext) \ +[KVM_RISCV_ISA_EXT_##ext] = "KVM_RISCV_ISA_EXT_" #ext + static const char *isa_ext_id_to_str(__u64 id) { /* reg_off is the offset into unsigned long kvm_isa_ext_arr[] */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); static const char * const kvm_isa_ext_reg_name[] = { - "KVM_RISCV_ISA_EXT_A", - "KVM_RISCV_ISA_EXT_C", - "KVM_RISCV_ISA_EXT_D", - "KVM_RISCV_ISA_EXT_F", - "KVM_RISCV_ISA_EXT_H", - "KVM_RISCV_ISA_EXT_I", - "KVM_RISCV_ISA_EXT_M", - "KVM_RISCV_ISA_EXT_SVPBMT", - "KVM_RISCV_ISA_EXT_SSTC", - "KVM_RISCV_ISA_EXT_SVINVAL", - "KVM_RISCV_ISA_EXT_ZIHINTPAUSE", - "KVM_RISCV_ISA_EXT_ZICBOM", - "KVM_RISCV_ISA_EXT_ZICBOZ", - "KVM_RISCV_ISA_EXT_ZBB", - "KVM_RISCV_ISA_EXT_SSAIA", - "KVM_RISCV_ISA_EXT_V", - "KVM_RISCV_ISA_EXT_SVNAPOT", - "KVM_RISCV_ISA_EXT_ZBA", - "KVM_RISCV_ISA_EXT_ZBS", - "KVM_RISCV_ISA_EXT_ZICNTR", - "KVM_RISCV_ISA_EXT_ZICSR", - "KVM_RISCV_ISA_EXT_ZIFENCEI", - "KVM_RISCV_ISA_EXT_ZIHPM", + KVM_ISA_EXT_ARR(A), + KVM_ISA_EXT_ARR(C), + KVM_ISA_EXT_ARR(D), + KVM_ISA_EXT_ARR(F), + KVM_ISA_EXT_ARR(H), + KVM_ISA_EXT_ARR(I), + KVM_ISA_EXT_ARR(M), + KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVINVAL), + KVM_ISA_EXT_ARR(SVNAPOT), + KVM_ISA_EXT_ARR(SVPBMT), + KVM_ISA_EXT_ARR(ZBA), + KVM_ISA_EXT_ARR(ZBB), + KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZICBOM), + KVM_ISA_EXT_ARR(ZICBOZ), + KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICSR), + KVM_ISA_EXT_ARR(ZIFENCEI), + KVM_ISA_EXT_ARR(ZIHINTPAUSE), + KVM_ISA_EXT_ARR(ZIHPM), }; if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) { @@ -353,19 +358,22 @@ static const char *isa_ext_id_to_str(__u64 id) return kvm_isa_ext_reg_name[reg_off]; } +#define KVM_SBI_EXT_ARR(ext) \ +[ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext + static const char *sbi_ext_single_id_to_str(__u64 reg_off) { /* reg_off is KVM_RISCV_SBI_EXT_ID */ static const char * const kvm_sbi_ext_reg_name[] = { - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL", - "KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR", + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), }; if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) { -- cgit v1.2.3 From 4d554e0226e6568c7b0b75418e7a24fefedbcefb Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 15 Sep 2023 21:25:27 +0530 Subject: KVM: riscv: selftests: Add senvcfg register to get-reg-list test We have a new senvcfg register in the general CSR ONE_REG interface so let us add it to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'tools') diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index a61b706a8778..6cec0ef75cc7 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -211,6 +211,8 @@ static const char *general_csr_id_to_str(__u64 reg_off) return RISCV_CSR_GENERAL(satp); case KVM_REG_RISCV_CSR_REG(scounteren): return RISCV_CSR_GENERAL(scounteren); + case KVM_REG_RISCV_CSR_REG(senvcfg): + return RISCV_CSR_GENERAL(senvcfg); } TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off); @@ -540,6 +542,7 @@ static __u64 base_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), -- cgit v1.2.3 From e1a8db0c9a0e7125c8e142c9eed7041ea37031d3 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 15 Sep 2023 21:52:12 +0530 Subject: KVM: riscv: selftests: Add smstateen registers to get-reg-list test We have a new smstateen registers as separate sub-type of CSR ONE_REG interface so let us add these registers to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'tools') diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 6cec0ef75cc7..625118d53b74 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -36,6 +36,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: @@ -186,6 +187,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id) "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")" #define RISCV_CSR_AIA(csr) \ "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_SMSTATEEN(csr) \ + "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" static const char *general_csr_id_to_str(__u64 reg_off) { @@ -243,6 +246,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off) return NULL; } +static const char *smstateen_csr_id_to_str(__u64 reg_off) +{ + /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ + switch (reg_off) { + case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0): + return RISCV_CSR_SMSTATEEN(sstateen0); + } + + TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off); + return NULL; +} + static const char *csr_id_to_str(const char *prefix, __u64 id) { __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); @@ -255,6 +270,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id) return general_csr_id_to_str(reg_off); case KVM_REG_RISCV_CSR_AIA: return aia_csr_id_to_str(reg_off); + case KVM_REG_RISCV_CSR_SMSTATEEN: + return smstateen_csr_id_to_str(reg_off); } TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype); @@ -332,6 +349,7 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(I), KVM_ISA_EXT_ARR(M), KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), @@ -637,6 +655,11 @@ static __u64 aia_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA, }; +static __u64 smstateen_regs[] = { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN, +}; + static __u64 fp_f_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]), KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]), @@ -744,6 +767,8 @@ static __u64 fp_d_regs[] = { {"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),} #define AIA_REGS_SUBLIST \ {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),} +#define SMSTATEEN_REGS_SUBLIST \ + {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),} #define FP_F_REGS_SUBLIST \ {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \ .regs_n = ARRAY_SIZE(fp_f_regs),} @@ -871,6 +896,14 @@ static struct vcpu_reg_list aia_config = { }, }; +static struct vcpu_reg_list smstateen_config = { + .sublists = { + BASE_SUBLIST, + SMSTATEEN_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list fp_f_config = { .sublists = { BASE_SUBLIST, @@ -903,6 +936,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &zifencei_config, &zihpm_config, &aia_config, + &smstateen_config, &fp_f_config, &fp_d_config, }; -- cgit v1.2.3 From 2b3f2b78ec93bdb1cfd8574158719d54263d50d6 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 15 Sep 2023 22:32:40 +0530 Subject: KVM: riscv: selftests: Add condops extensions to get-reg-list test We have a new conditional operations related ISA extensions so let us add these extensions to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'tools') diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 625118d53b74..77dc5221c465 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -48,6 +48,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: @@ -361,6 +362,7 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(ZICBOM), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), KVM_ISA_EXT_ARR(ZIFENCEI), KVM_ISA_EXT_ARR(ZIHINTPAUSE), @@ -632,6 +634,10 @@ static __u64 zicntr_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR, }; +static __u64 zicond_regs[] = { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND, +}; + static __u64 zicsr_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR, }; @@ -759,6 +765,8 @@ static __u64 fp_d_regs[] = { {"zbs", .feature = KVM_RISCV_ISA_EXT_ZBS, .regs = zbs_regs, .regs_n = ARRAY_SIZE(zbs_regs),} #define ZICNTR_REGS_SUBLIST \ {"zicntr", .feature = KVM_RISCV_ISA_EXT_ZICNTR, .regs = zicntr_regs, .regs_n = ARRAY_SIZE(zicntr_regs),} +#define ZICOND_REGS_SUBLIST \ + {"zicond", .feature = KVM_RISCV_ISA_EXT_ZICOND, .regs = zicond_regs, .regs_n = ARRAY_SIZE(zicond_regs),} #define ZICSR_REGS_SUBLIST \ {"zicsr", .feature = KVM_RISCV_ISA_EXT_ZICSR, .regs = zicsr_regs, .regs_n = ARRAY_SIZE(zicsr_regs),} #define ZIFENCEI_REGS_SUBLIST \ @@ -864,6 +872,14 @@ static struct vcpu_reg_list zicntr_config = { }, }; +static struct vcpu_reg_list zicond_config = { + .sublists = { + BASE_SUBLIST, + ZICOND_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list zicsr_config = { .sublists = { BASE_SUBLIST, @@ -932,6 +948,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &zbb_config, &zbs_config, &zicntr_config, + &zicond_config, &zicsr_config, &zifencei_config, &zihpm_config, -- cgit v1.2.3 From 62d0c458f828949dd01bfe41daf3bed73ab9e288 Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Wed, 20 Sep 2023 16:37:14 +0200 Subject: KVM: riscv: selftests: get-reg-list print_reg should never fail When outputting the "new" register list we want to print all of the new registers, decoding as much as possible of each of them. Also, we don't want to assert while listing registers with '--list'. We output "/* UNKNOWN */" after each new register (which we were already doing for some), which should be enough. Signed-off-by: Andrew Jones Reviewed-by: Haibo Xu Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 93 +++++++++++------------- 1 file changed, 42 insertions(+), 51 deletions(-) (limited to 'tools') diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 77dc5221c465..234006d035c9 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -116,11 +116,13 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) } } -static const char *config_id_to_str(__u64 id) +static const char *config_id_to_str(const char *prefix, __u64 id) { /* reg_off is the offset into struct kvm_riscv_config */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG); + switch (reg_off) { case KVM_REG_RISCV_CONFIG_REG(isa): return "KVM_REG_RISCV_CONFIG_REG(isa)"; @@ -138,11 +140,7 @@ static const char *config_id_to_str(__u64 id) return "KVM_REG_RISCV_CONFIG_REG(satp_mode)"; } - /* - * Config regs would grow regularly with new pseudo reg added, so - * just show raw id to indicate a new pseudo config reg. - */ - return strdup_printf("KVM_REG_RISCV_CONFIG_REG(%lld) /* UNKNOWN */", reg_off); + return strdup_printf("%lld /* UNKNOWN */", reg_off); } static const char *core_id_to_str(const char *prefix, __u64 id) @@ -150,6 +148,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id) /* reg_off is the offset into struct kvm_riscv_core */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE); + switch (reg_off) { case KVM_REG_RISCV_CORE_REG(regs.pc): return "KVM_REG_RISCV_CORE_REG(regs.pc)"; @@ -180,8 +180,7 @@ static const char *core_id_to_str(const char *prefix, __u64 id) return "KVM_REG_RISCV_CORE_REG(mode)"; } - TEST_FAIL("%s: Unknown core reg id: 0x%llx", prefix, id); - return NULL; + return strdup_printf("%lld /* UNKNOWN */", reg_off); } #define RISCV_CSR_GENERAL(csr) \ @@ -219,8 +218,7 @@ static const char *general_csr_id_to_str(__u64 reg_off) return RISCV_CSR_GENERAL(senvcfg); } - TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off); - return NULL; + return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off); } static const char *aia_csr_id_to_str(__u64 reg_off) @@ -243,8 +241,7 @@ static const char *aia_csr_id_to_str(__u64 reg_off) return RISCV_CSR_AIA(iprio2h); } - TEST_FAIL("Unknown aia csr reg: 0x%llx", reg_off); - return NULL; + return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off); } static const char *smstateen_csr_id_to_str(__u64 reg_off) @@ -264,6 +261,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id) __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR); + reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; switch (reg_subtype) { @@ -275,8 +274,7 @@ static const char *csr_id_to_str(const char *prefix, __u64 id) return smstateen_csr_id_to_str(reg_off); } - TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype); - return NULL; + return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); } static const char *timer_id_to_str(const char *prefix, __u64 id) @@ -284,6 +282,8 @@ static const char *timer_id_to_str(const char *prefix, __u64 id) /* reg_off is the offset into struct kvm_riscv_timer */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER); + switch (reg_off) { case KVM_REG_RISCV_TIMER_REG(frequency): return "KVM_REG_RISCV_TIMER_REG(frequency)"; @@ -295,8 +295,7 @@ static const char *timer_id_to_str(const char *prefix, __u64 id) return "KVM_REG_RISCV_TIMER_REG(state)"; } - TEST_FAIL("%s: Unknown timer reg id: 0x%llx", prefix, id); - return NULL; + return strdup_printf("%lld /* UNKNOWN */", reg_off); } static const char *fp_f_id_to_str(const char *prefix, __u64 id) @@ -304,6 +303,8 @@ static const char *fp_f_id_to_str(const char *prefix, __u64 id) /* reg_off is the offset into struct __riscv_f_ext_state */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F); + switch (reg_off) { case KVM_REG_RISCV_FP_F_REG(f[0]) ... KVM_REG_RISCV_FP_F_REG(f[31]): @@ -312,8 +313,7 @@ static const char *fp_f_id_to_str(const char *prefix, __u64 id) return "KVM_REG_RISCV_FP_F_REG(fcsr)"; } - TEST_FAIL("%s: Unknown fp_f reg id: 0x%llx", prefix, id); - return NULL; + return strdup_printf("%lld /* UNKNOWN */", reg_off); } static const char *fp_d_id_to_str(const char *prefix, __u64 id) @@ -321,6 +321,8 @@ static const char *fp_d_id_to_str(const char *prefix, __u64 id) /* reg_off is the offset into struct __riscv_d_ext_state */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D); + switch (reg_off) { case KVM_REG_RISCV_FP_D_REG(f[0]) ... KVM_REG_RISCV_FP_D_REG(f[31]): @@ -329,18 +331,19 @@ static const char *fp_d_id_to_str(const char *prefix, __u64 id) return "KVM_REG_RISCV_FP_D_REG(fcsr)"; } - TEST_FAIL("%s: Unknown fp_d reg id: 0x%llx", prefix, id); - return NULL; + return strdup_printf("%lld /* UNKNOWN */", reg_off); } #define KVM_ISA_EXT_ARR(ext) \ [KVM_RISCV_ISA_EXT_##ext] = "KVM_RISCV_ISA_EXT_" #ext -static const char *isa_ext_id_to_str(__u64 id) +static const char *isa_ext_id_to_str(const char *prefix, __u64 id) { /* reg_off is the offset into unsigned long kvm_isa_ext_arr[] */ __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT); + static const char * const kvm_isa_ext_reg_name[] = { KVM_ISA_EXT_ARR(A), KVM_ISA_EXT_ARR(C), @@ -369,13 +372,8 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(ZIHPM), }; - if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) { - /* - * isa_ext regs would grow regularly with new isa extension added, so - * just show "reg" to indicate a new extension. - */ + if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) return strdup_printf("%lld /* UNKNOWN */", reg_off); - } return kvm_isa_ext_reg_name[reg_off]; } @@ -398,35 +396,27 @@ static const char *sbi_ext_single_id_to_str(__u64 reg_off) KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), }; - if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) { - /* - * sbi_ext regs would grow regularly with new sbi extension added, so - * just show "reg" to indicate a new extension. - */ + if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off); - } return kvm_sbi_ext_reg_name[reg_off]; } static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) { - if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST) { - /* - * sbi_ext regs would grow regularly with new sbi extension added, so - * just show "reg" to indicate a new extension. - */ - return strdup_printf("%lld /* UNKNOWN */", reg_off); - } + const char *unknown = ""; + + if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST) + unknown = " /* UNKNOWN */"; switch (reg_subtype) { case KVM_REG_RISCV_SBI_MULTI_EN: - return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld", reg_off); + return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown); case KVM_REG_RISCV_SBI_MULTI_DIS: - return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld", reg_off); + return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown); } - return NULL; + return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); } static const char *sbi_ext_id_to_str(const char *prefix, __u64 id) @@ -434,6 +424,8 @@ static const char *sbi_ext_id_to_str(const char *prefix, __u64 id) __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; + assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_EXT); + reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; switch (reg_subtype) { @@ -444,8 +436,7 @@ static const char *sbi_ext_id_to_str(const char *prefix, __u64 id) return sbi_ext_multi_id_to_str(reg_subtype, reg_off); } - TEST_FAIL("%s: Unknown sbi ext subtype: 0x%llx", prefix, reg_subtype); - return NULL; + return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); } void print_reg(const char *prefix, __u64 id) @@ -466,14 +457,14 @@ void print_reg(const char *prefix, __u64 id) reg_size = "KVM_REG_SIZE_U128"; break; default: - TEST_FAIL("%s: Unexpected reg size: 0x%llx in reg id: 0x%llx", - prefix, (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id); + printf("\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */,", + (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id & REG_MASK); } switch (id & KVM_REG_RISCV_TYPE_MASK) { case KVM_REG_RISCV_CONFIG: printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n", - reg_size, config_id_to_str(id)); + reg_size, config_id_to_str(prefix, id)); break; case KVM_REG_RISCV_CORE: printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n", @@ -497,15 +488,15 @@ void print_reg(const char *prefix, __u64 id) break; case KVM_REG_RISCV_ISA_EXT: printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n", - reg_size, isa_ext_id_to_str(id)); + reg_size, isa_ext_id_to_str(prefix, id)); break; case KVM_REG_RISCV_SBI_EXT: printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n", reg_size, sbi_ext_id_to_str(prefix, id)); break; default: - TEST_FAIL("%s: Unexpected reg type: 0x%llx in reg id: 0x%llx", prefix, - (id & KVM_REG_RISCV_TYPE_MASK) >> KVM_REG_RISCV_TYPE_SHIFT, id); + printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,", + reg_size, id & REG_MASK); } } -- cgit v1.2.3 From d9c00f44e5de542340cce1d09e2c990e16c0ed3a Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 20 Oct 2023 12:38:27 +0530 Subject: KVM: riscv: selftests: Add SBI DBCN extension to get-reg-list test We have a new SBI debug console (DBCN) extension supported by in-kernel KVM so let us add this extension to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tools') diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 234006d035c9..6bedaea95395 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -394,6 +394,7 @@ static const char *sbi_ext_single_id_to_str(__u64 reg_off) KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN), }; if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) @@ -567,6 +568,7 @@ static __u64 base_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR, + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_EN | 0, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_DIS | 0, }; -- cgit v1.2.3