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Allwinner V3s Camera Sensor Interface
-------------------------------------
Allwinner V3s SoC features a CSI module(CSI1) with parallel interface.
Required properties:
- compatible: value must be one of:
* "allwinner,sun6i-a31-csi"
* "allwinner,sun8i-h3-csi", "allwinner,sun6i-a31-csi"
* "allwinner,sun8i-v3s-csi"
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the CSI
* bus: the CSI interface clock
* mod: the CSI module clock
* ram: the CSI DRAM clock
- clock-names: the clock names mentioned above
- resets: phandles to the reset line driving the CSI
The CSI node should contain one 'port' child node with one child 'endpoint'
node, according to the bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Endpoint node properties for CSI
---------------------------------
See the video-interfaces.txt for a detailed description of these properties.
- remote-endpoint : (required) a phandle to the bus receiver's endpoint
node
- bus-width: : (required) must be 8, 10, 12 or 16
- pclk-sample : (optional) (default: sample on falling edge)
- hsync-active : (required; parallel-only)
- vsync-active : (required; parallel-only)
Example:
csi1: csi@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI1_SCLK>,
<&ccu CLK_DRAM_CSI>;
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
port {
/* Parallel bus endpoint */
csi1_ep: endpoint {
remote-endpoint = <&adv7611_ep>;
bus-width = <16>;
/* If hsync-active/vsync-active are missing,
embedded BT.656 sync is used */
hsync-active = <0>; /* Active low */
vsync-active = <0>; /* Active low */
pclk-sample = <1>; /* Rising */
};
};
};
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