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authorAnton Blanchard <anton@samba.org>2005-09-06 14:50:48 +1000
committerPaul Mackerras <paulus@samba.org>2005-09-06 16:09:20 +1000
commit8530935d384bef1467ba76e1f4382f0f8b3c899d (patch)
treec96ed2a5f10da98ed5726fd01c59e58cb09ad7c7
parentfd5b4377eacac42293b1a349dbb0f9892bf7f74a (diff)
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[PATCH] ppc64: remove CPU_FTR_PMC8
Remove the CPU_FTR_PMC8 feature now we encode the number of PMCs directly. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/ppc64/kernel/cputable.c24
-rw-r--r--include/asm-ppc64/cputable.h2
2 files changed, 12 insertions, 14 deletions
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index a20960e47105..25ab72323c58 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -54,8 +54,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x00400000,
.cpu_name = "POWER3 (630)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_PMC8,
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -67,8 +66,7 @@ struct cpu_spec cpu_specs[] = {
.pvr_value = 0x00410000,
.cpu_name = "POWER3 (630+)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_PMC8,
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -81,7 +79,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "RS64-II (northstar)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -94,7 +92,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "RS64-III (pulsar)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -107,7 +105,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "RS64-III (icestar)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -120,7 +118,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "RS64-IV (sstar)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -133,7 +131,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "POWER4 (gp)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -146,7 +144,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_name = "POWER4+ (gq)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -160,7 +158,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+ CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -175,7 +173,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+ CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
@@ -190,7 +188,7 @@ struct cpu_spec cpu_specs[] = {
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
+ CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
index 0c8affc657fa..80b907727a79 100644
--- a/include/asm-ppc64/cputable.h
+++ b/include/asm-ppc64/cputable.h
@@ -98,7 +98,7 @@ static inline unsigned long cpu_has_feature(unsigned long feature)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
-#define CPU_FTR_PMC8 ASM_CONST(0x0000008000000000)
+/* unused ASM_CONST(0x0000008000000000) */
#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)