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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-03-19 16:23:55 +1100
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-03-19 16:23:55 +1100
commitd6a8536a93a3d14b6e5e3e3a59b9fb2bca6e8df2 (patch)
tree14de9959c93e56a8d165670faaa7ea3699da7f8e
parentbca14dd14f3b0c5e3e2d1d314679f85b67871365 (diff)
parent9d296cfa69b3d4abc9d556986d544f0727988eed (diff)
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Merge commit 'kumar/merge' into merge
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h6
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S3
2 files changed, 3 insertions, 6 deletions
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index aea714797590..d553bbeb726c 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -25,7 +25,7 @@
#define PPC_INST_LDARX 0x7c0000a8
#define PPC_INST_LSWI 0x7c0004aa
#define PPC_INST_LSWX 0x7c00042a
-#define PPC_INST_LWARX 0x7c000029
+#define PPC_INST_LWARX 0x7c000028
#define PPC_INST_LWSYNC 0x7c2004ac
#define PPC_INST_LXVD2X 0x7c000698
#define PPC_INST_MCRXR 0x7c000400
@@ -62,8 +62,8 @@
#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
#define __PPC_WC(w) (((w) & 0x3) << 21)
/*
- * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have
- * any side effects on all 32bit processors, we can do this all the time.
+ * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
+ * larx with EH set as an illegal instruction.
*/
#ifdef CONFIG_PPC64
#define __PPC_EH(eh) (((eh) & 0x1) << 0)
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 25793bb0e782..a7cf4934342c 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -747,9 +747,6 @@ finish_tlb_load:
#else
rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
#endif
-#ifdef CONFIG_SMP
- ori r12, r12, MAS2_M
-#endif
mtspr SPRN_MAS2, r12
#ifdef CONFIG_PTE_64BIT