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| author | Ralf Baechle <ralf@ongar.mips.com> | 2005-12-09 12:20:49 +0000 |
|---|---|---|
| committer | <ralf@denk.linux-mips.net> | 2006-01-10 13:39:07 +0000 |
| commit | 0401572a9b9b2f368176b6e53f53004fd048a566 (patch) | |
| tree | ac150d269955aeba9eff5bdaa2835626510c9180 | |
| parent | 11e6df65dc2bae8e7ad17ff81611ddc850b279cd (diff) | |
| download | linux-0401572a9b9b2f368176b6e53f53004fd048a566.tar.gz linux-0401572a9b9b2f368176b6e53f53004fd048a566.tar.bz2 linux-0401572a9b9b2f368176b6e53f53004fd048a566.zip | |
MIPS: Reorganize ISA constants strictly as bitmasks.
Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
| -rw-r--r-- | include/asm-mips/cpu-features.h | 45 | ||||
| -rw-r--r-- | include/asm-mips/cpu.h | 17 |
2 files changed, 31 insertions, 31 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index f8be4a470754..78c9cc2735d5 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -116,6 +116,27 @@ #endif #endif +# ifndef cpu_has_mips32r1 +# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) +# endif +# ifndef cpu_has_mips32r2 +# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) +# endif +# ifndef cpu_has_mips64r1 +# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) +# endif +# ifndef cpu_has_mips64r2 +# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) +# endif + +/* + * Shortcuts ... + */ +#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) +#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) +#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) +#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) + #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif @@ -144,18 +165,6 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 0 # endif -# ifndef cpu_has_mips32r1 -# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) -# endif -# ifndef cpu_has_mips32r2 -# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) -# endif -# ifndef cpu_has_mips64r1 -# define cpu_has_mips64r1 0 -# endif -# ifndef cpu_has_mips64r2 -# define cpu_has_mips64r2 0 -# endif #endif #ifdef CONFIG_64BIT @@ -174,18 +183,6 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 1 # endif -# ifndef cpu_has_mips32r1 -# define cpu_has_mips32r1 0 -# endif -# ifndef cpu_has_mips32r2 -# define cpu_has_mips32r2 0 -# endif -# ifndef cpu_has_mips64r1 -# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) -# endif -# ifndef cpu_has_mips64r2 -# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) -# endif #endif #ifdef CONFIG_CPU_MIPSR2 diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 48c37c46053a..934e063e79f1 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -202,17 +202,20 @@ * ISA Level encodings * */ -#define MIPS_CPU_ISA_64BIT 0x00008000 - #define MIPS_CPU_ISA_I 0x00000001 #define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III (0x00000003 | MIPS_CPU_ISA_64BIT) -#define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT) -#define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT) +#define MIPS_CPU_ISA_III 0x00000003 +#define MIPS_CPU_ISA_IV 0x00000004 +#define MIPS_CPU_ISA_V 0x00000005 #define MIPS_CPU_ISA_M32R1 0x00000020 #define MIPS_CPU_ISA_M32R2 0x00000040 -#define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT) -#define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT) +#define MIPS_CPU_ISA_M64R1 0x00000080 +#define MIPS_CPU_ISA_M64R2 0x00000100 + +#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ + MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) +#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ + MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) /* * CPU Option encodings |